| V1 |
|
100.00% |
| V2 |
|
81.25% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 25.000s | 16623.963us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 8.000s | 59.653us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 7.000s | 13.408us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 7.000s | 288.006us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 6.000s | 83.921us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 4.000s | 173.004us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 7.000s | 13.408us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 6.000s | 83.921us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 3.000s | 606.211us | 0 | 1 | 0.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 6.000s | 436.531us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 5.000s | 451.970us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 9.000s | 747.466us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 50.366us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 8.000s | 17.151us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 11.000s | 244.572us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 11.000s | 244.572us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 8.000s | 59.653us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 7.000s | 13.408us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 6.000s | 83.921us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 5.000s | 19.148us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 8.000s | 59.653us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 7.000s | 13.408us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 6.000s | 83.921us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 5.000s | 19.148us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 8.000s | 317.077us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 2.000s | 18.091us | 1 | 1 | 100.00 | |