Simulation Results: rom_ctrl

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.69 %
  • code
  • 98.40 %
  • assert
  • 95.49 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 94.80 %
  • toggle
  • 98.83 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.620s 1162.311us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.270s 221.265us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.060s 288.969us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.820s 557.082us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.590s 557.458us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.040s 995.085us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.060s 288.969us 1 1 100.00
rom_ctrl_csr_aliasing 6.590s 557.458us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.310s 433.242us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.990s 291.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.800s 306.830us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 30.170s 1082.121us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.350s 6642.438us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.690s 370.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.120s 302.152us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.120s 302.152us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.270s 221.265us 1 1 100.00
rom_ctrl_csr_rw 7.060s 288.969us 1 1 100.00
rom_ctrl_csr_aliasing 6.590s 557.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.660s 727.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.270s 221.265us 1 1 100.00
rom_ctrl_csr_rw 7.060s 288.969us 1 1 100.00
rom_ctrl_csr_aliasing 6.590s 557.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.660s 727.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.560s 6893.043us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
rom_ctrl_tl_intg_err 95.670s 2414.768us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.620s 1162.311us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.620s 1162.311us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.620s 1162.311us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.670s 2414.768us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
rom_ctrl_kmac_err_chk 11.350s 6642.438us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.740s 5852.406us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.560s 6893.043us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 220.240s 1173.983us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 96.300s 8406.635us 1 1 100.00