Simulation Results: rv_dm

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.92 %
  • code
  • 71.96 %
  • assert
  • 96.09 %
  • func
  • 62.72 %
  • line
  • 90.53 %
  • branch
  • 74.36 %
  • cond
  • 72.98 %
  • toggle
  • 68.82 %
  • FSM
  • 53.12 %
Validation stages
V1
90.32%
V2
57.14%
V2S
91.67%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
rv_dm_smoke 13.420s 10252.687us 0 1 0.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.880s 330.560us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.420s 230.920us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 24.560s 24509.311us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.240s 698.752us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 6.320s 2399.259us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 10.700s 4952.672us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 7.700s 14462.334us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 54.650s 47490.852us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.430s 584.277us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.360s 181.550us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.870s 707.029us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.130s 124.746us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.820s 551.183us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.020s 681.308us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.270s 391.870us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.770s 1436.968us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.430s 584.277us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.590s 282.444us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.430s 985.501us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.870s 707.029us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.920s 167.548us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.570s 106.111us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 2.380s 253.332us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 19.870s 795.584us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 49.130s 3467.236us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 1.260s 95.065us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 49.130s 3467.236us 1 1 100.00
rv_dm_csr_rw 2.380s 253.332us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.870s 97.302us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.830s 63.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 0 1 0.00
rv_dm_smoke 13.420s 10252.687us 0 1 0.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.250s 338.206us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.770s 210.998us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.860s 109.636us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 3.220s 1078.960us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 405.730s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 639.930s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 517.530s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 91.320s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 1.070s 80.144us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.780s 997.903us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.900s 193.277us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.920s 59.226us 0 1 0.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm 20.130s 20902.329us 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.230s 97.074us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.900s 124.422us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 3.450s 1301.692us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.710s 188.262us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.050s 76.203us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.050s 76.203us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 49.130s 3467.236us 1 1 100.00
rv_dm_csr_hw_reset 1.570s 106.111us 1 1 100.00
rv_dm_csr_rw 2.380s 253.332us 1 1 100.00
rv_dm_same_csr_outstanding 3.380s 391.749us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 49.130s 3467.236us 1 1 100.00
rv_dm_csr_hw_reset 1.570s 106.111us 1 1 100.00
rv_dm_csr_rw 2.380s 253.332us 1 1 100.00
rv_dm_same_csr_outstanding 3.380s 391.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 2.520s 823.664us 1 1 100.00
rv_dm_tl_intg_err 8.200s 3905.791us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 8.200s 3905.791us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.780s 997.903us 1 1 100.00
rv_dm_debug_disabled 0.980s 65.331us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.780s 997.903us 1 1 100.00
rv_dm_debug_disabled 0.980s 65.331us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 1 0.00
rv_dm_smoke 13.420s 10252.687us 0 1 0.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.330s 197.936us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.900s 80.205us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.900s 80.205us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.330s 197.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.870s 59.805us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 650.810s 300000.000us 0 1 0.00