Simulation Results: spi_device

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.63 %
  • code
  • 93.26 %
  • assert
  • 94.30 %
  • func
  • 72.32 %
  • line
  • 99.10 %
  • branch
  • 98.39 %
  • cond
  • 95.90 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 146.010s 19777.070us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.010s 80.578us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.530s 78.842us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.470s 3671.235us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.300s 2449.790us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.140s 198.388us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.530s 78.842us 1 1 100.00
spi_device_csr_aliasing 6.300s 2449.790us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 13.678us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.520s 76.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.880s 21.951us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.700s 7.542us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.720s 6.886us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.220s 73.642us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.220s 73.642us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 7.860s 2528.257us 1 1 100.00
spi_device_tpm_sts_read 0.840s 37.880us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 12.850s 1962.668us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.780s 806.779us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.190s 72.850us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.190s 72.850us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.560s 3534.172us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.560s 3534.172us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.560s 3534.172us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.560s 3534.172us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.560s 3534.172us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.150s 15017.294us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.740s 4332.976us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.740s 4332.976us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.740s 4332.976us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.810s 406.032us 1 1 100.00
spi_device_read_buffer_direct 7.840s 2983.202us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.740s 4332.976us 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 22.680s 13951.097us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.640s 83.502us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.640s 83.502us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 146.010s 19777.070us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 553.110s 91818.202us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 61.910s 17047.567us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.750s 114.152us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.760s 46.016us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.770s 109.819us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.770s 109.819us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 80.578us 1 1 100.00
spi_device_csr_rw 1.530s 78.842us 1 1 100.00
spi_device_csr_aliasing 6.300s 2449.790us 1 1 100.00
spi_device_same_csr_outstanding 1.750s 114.532us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 80.578us 1 1 100.00
spi_device_csr_rw 1.530s 78.842us 1 1 100.00
spi_device_csr_aliasing 6.300s 2449.790us 1 1 100.00
spi_device_same_csr_outstanding 1.750s 114.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 15.420s 794.780us 1 1 100.00
spi_device_sec_cm 1.370s 71.284us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.420s 794.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 49.990s 55371.356us 1 1 100.00