Simulation Results: spi_host

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.81 %
  • code
  • 95.02 %
  • assert
  • 92.50 %
  • func
  • 87.92 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 5.000s 379.543us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 15.960us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 63.623us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 1008.615us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 123.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 32.197us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 63.623us 1 1 100.00
spi_host_csr_aliasing 1.000s 123.813us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 15.419us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 59.034us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 181.634us 1 1 100.00
spi_host_error_cmd 2.000s 46.779us 1 1 100.00
spi_host_event 14.000s 1817.245us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 172.637us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 172.637us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 172.637us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 145.829us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 79.114us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 172.637us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 172.637us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 5.000s 379.543us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 5.000s 379.543us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 17.000s 1452.728us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 117.606us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 61.000s 7315.887us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 7.000s 4674.090us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 181.634us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 20.705us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 19.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 34.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 34.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 15.960us 1 1 100.00
spi_host_csr_rw 2.000s 63.623us 1 1 100.00
spi_host_csr_aliasing 1.000s 123.813us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 159.338us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 15.960us 1 1 100.00
spi_host_csr_rw 2.000s 63.623us 1 1 100.00
spi_host_csr_aliasing 1.000s 123.813us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 159.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 211.507us 1 1 100.00
spi_host_tl_intg_err 2.000s 58.011us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 58.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 259.000s 13589.199us 1 1 100.00