Simulation Results: sram_ctrl

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.71 %
  • code
  • 93.83 %
  • assert
  • 95.69 %
  • func
  • 94.62 %
  • line
  • 98.66 %
  • branch
  • 96.78 %
  • cond
  • 92.53 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 10.440s 500.063us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.680s 23.238us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.660s 15.509us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.040s 32.048us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 22.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.460s 702.970us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.660s 15.509us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 22.817us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 265.630s 43091.434us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 113.980s 35009.383us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 523.480s 24332.461us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 251.640s 11825.978us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1088.080s 599942.559us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 594.040s 45318.077us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 45.180s 13053.492us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 457.750s 59240.716us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.020s 1728.360us 1 1 100.00
sram_ctrl_partial_access_b2b 277.030s 14323.900us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 19.430s 1501.084us 1 1 100.00
sram_ctrl_throughput_w_partial_write 19.160s 756.122us 1 1 100.00
sram_ctrl_throughput_w_readback 22.780s 881.525us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 24.620s 1033.717us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.470s 381.565us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2485.220s 210433.659us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.640s 15.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.980s 76.288us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.980s 76.288us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.680s 23.238us 1 1 100.00
sram_ctrl_csr_rw 0.660s 15.509us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 22.817us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 81.117us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.680s 23.238us 1 1 100.00
sram_ctrl_csr_rw 0.660s 15.509us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 22.817us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 81.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.630s 3881.652us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
sram_ctrl_tl_intg_err 1.610s 1178.283us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.610s 1178.283us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 24.620s 1033.717us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 24.620s 1033.717us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.660s 15.509us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 457.750s 59240.716us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 457.750s 59240.716us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 457.750s 59240.716us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 45.180s 13053.492us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.970s 2814.119us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.630s 3881.652us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.850s 5994.601us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 10.440s 500.063us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 10.440s 500.063us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 457.750s 59240.716us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 45.180s 13053.492us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 10.440s 500.063us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.970s 8.695us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.750s 9859.569us 1 1 100.00