Simulation Results: sram_ctrl

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.43 %
  • code
  • 89.08 %
  • assert
  • 95.65 %
  • func
  • 95.55 %
  • line
  • 97.21 %
  • branch
  • 94.19 %
  • cond
  • 91.92 %
  • toggle
  • 90.66 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 10.660s 2726.175us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.630s 40.952us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 14.948us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.390s 323.579us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 95.262us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.560s 396.373us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 14.948us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 95.262us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.790s 95.489us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.800s 154.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 170.330s 12470.252us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 168.940s 9402.804us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 24.450s 1678.643us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 666.630s 16378.343us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.770s 478.738us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 401.720s 16777.839us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.020s 2069.350us 1 1 100.00
sram_ctrl_partial_access_b2b 264.050s 13503.586us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.260s 60.079us 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.500s 129.517us 1 1 100.00
sram_ctrl_throughput_w_readback 2.140s 240.871us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 570.320s 18200.714us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.830s 50.528us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1813.840s 121771.596us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.780s 41.649us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.790s 229.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.790s 229.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.630s 40.952us 1 1 100.00
sram_ctrl_csr_rw 0.740s 14.948us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 95.262us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 92.187us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.630s 40.952us 1 1 100.00
sram_ctrl_csr_rw 0.740s 14.948us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 95.262us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 92.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 334.497us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
sram_ctrl_tl_intg_err 1.290s 229.580us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.290s 229.580us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 570.320s 18200.714us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 570.320s 18200.714us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 14.948us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 401.720s 16777.839us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 401.720s 16777.839us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 401.720s 16777.839us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.770s 478.738us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.190s 52.192us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 334.497us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.870s 90.144us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 10.660s 2726.175us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 10.660s 2726.175us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 401.720s 16777.839us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.770s 478.738us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 10.660s 2726.175us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.640s 12.325us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 214.300s 1754.941us 1 1 100.00