Simulation Results: uart

 
04/12/2025 16:02:27 sha: 1fd34a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.73 %
  • code
  • 95.87 %
  • assert
  • 97.12 %
  • func
  • 52.20 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 5.720s 6075.944us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.840s 13.857us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.860s 18.992us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.520s 96.059us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.940s 30.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.980s 63.337us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.860s 18.992us 1 1 100.00
uart_csr_aliasing 0.940s 30.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.740s 49888.770us 1 1 100.00
parity 2 2 100.00
uart_smoke 5.720s 6075.944us 1 1 100.00
uart_tx_rx 29.740s 49888.770us 1 1 100.00
parity_error 2 2 100.00
uart_intr 43.300s 45311.144us 1 1 100.00
uart_rx_parity_err 107.540s 65375.336us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.740s 49888.770us 1 1 100.00
uart_intr 43.300s 45311.144us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 13.630s 20955.193us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.140s 41594.034us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 15.760s 19685.189us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 43.300s 45311.144us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 43.300s 45311.144us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 43.300s 45311.144us 1 1 100.00
perf 1 1 100.00
uart_perf 224.950s 27948.629us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.520s 5446.677us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.520s 5446.677us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.410s 1295.526us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 14.460s 46569.396us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.780s 8267.478us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.280s 6205.699us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 273.250s 247592.704us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 188.180s 279473.440us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.610s 21.317us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.800s 38.221us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.390s 78.259us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.390s 78.259us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.840s 13.857us 1 1 100.00
uart_csr_rw 0.860s 18.992us 1 1 100.00
uart_csr_aliasing 0.940s 30.541us 1 1 100.00
uart_same_csr_outstanding 0.700s 18.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.840s 13.857us 1 1 100.00
uart_csr_rw 0.860s 18.992us 1 1 100.00
uart_csr_aliasing 0.940s 30.541us 1 1 100.00
uart_same_csr_outstanding 0.700s 18.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.620s 182.440us 1 1 100.00
uart_sec_cm 1.200s 105.926us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.620s 182.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.270s 4454.107us 1 1 100.00