Simulation Results: ac_range_check

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.72 %
  • code
  • 92.98 %
  • assert
  • 97.63 %
  • func
  • 57.56 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 80.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 26.000s 524.807us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 34.000s 2638.311us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 34.502us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 262.730us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 29.000s 1679.335us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5242.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 25.108us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 262.730us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5242.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 48.337us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 25.000s 477.391us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 103.000s 6225.667us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 132.740us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 24.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 104.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 104.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 34.502us 1 1 100.00
ac_range_check_csr_rw 2.000s 262.730us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5242.533us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 217.392us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 34.502us 1 1 100.00
ac_range_check_csr_rw 2.000s 262.730us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5242.533us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 217.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1701.653us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1701.653us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1701.653us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1701.653us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 85.000s 19619.868us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 30.779us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 618.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 255.000s 1468.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 26.000s 7824.163us 1 1 100.00

Error Messages

   Test seed line log context