Simulation Results: alert_handler

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 91.73 %
  • assert
  • 97.93 %
  • func
  • 71.49 %
  • line
  • 99.66 %
  • branch
  • 99.75 %
  • cond
  • 92.99 %
  • toggle
  • 95.28 %
  • FSM
  • 70.97 %
Validation stages
V1
100.00%
V2
91.67%
V2S
96.30%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 9.200s 272.988us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.460s 156.275us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 91.270s 3425.243us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 206.080s 3801.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.020s 39.626us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.460s 156.275us 1 1 100.00
alert_handler_csr_aliasing 206.080s 3801.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 226.320s 10835.235us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 14.670s 1439.785us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 632.120s 42391.717us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.160s 206.330us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 16.450s 1318.835us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 40.670s 4023.601us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 17.010s 2409.774us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 753.210s 44933.264us 0 1 0.00
alert_handler_lpg_stub_clk 1251.270s 29895.191us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 592.210s 32758.668us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 92.320s 6313.581us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.040s 21.075us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.330s 7.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.630s 216.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.630s 216.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 9.200s 272.988us 1 1 100.00
alert_handler_csr_rw 5.460s 156.275us 1 1 100.00
alert_handler_csr_aliasing 206.080s 3801.156us 1 1 100.00
alert_handler_same_csr_outstanding 18.010s 362.793us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 9.200s 272.988us 1 1 100.00
alert_handler_csr_rw 5.460s 156.275us 1 1 100.00
alert_handler_csr_aliasing 206.080s 3801.156us 1 1 100.00
alert_handler_same_csr_outstanding 18.010s 362.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 132.450s 9594.528us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 132.450s 9594.528us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 132.450s 9594.528us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 132.450s 9594.528us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 291.120s 10830.421us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 3.400s 102.315us 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.400s 102.315us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 132.450s 9594.528us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 25.990s 1183.190us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.160s 206.330us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 753.210s 44933.264us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.160s 206.330us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 632.120s 42391.717us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 632.120s 42391.717us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 18.380s 3187.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 6.670s 105.346us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 29987736125440843700969376963562307258801375348810500991124063656096131688069 78
UVM_ERROR @ 2409773838 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2409773838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_lpg 110346815204867984657409639411146132433046421472849081952539355564292821495796 78
UVM_ERROR @ 44933263695 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 44933263695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 45935767054857772663322143039350985454755343725804888646833680021937722775304 80
UVM_ERROR @ 105345546 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 105345546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---