Simulation Results: clkmgr

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.56 %
  • code
  • 69.03 %
  • assert
  • 86.36 %
  • func
  • 68.29 %
  • line
  • 82.09 %
  • branch
  • 87.58 %
  • cond
  • 77.35 %
  • toggle
  • 98.11 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
57.89%
V2S
70.59%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.080s 25.521us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.020s 48.691us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 6.770s 702.439us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.950s 15.692us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 5.898us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
clkmgr_csr_aliasing 0.950s 15.692us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.960s 19.652us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.160s 195.363us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.700s 125.077us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.080s 25.521us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.850s 6.538us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.790s 12.520us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.850s 6.538us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.080s 57.805us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 15.465us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.900s 236.224us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.900s 236.224us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.020s 48.691us 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
clkmgr_csr_aliasing 0.950s 15.692us 0 1 0.00
clkmgr_same_csr_outstanding 1.460s 102.669us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.020s 48.691us 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
clkmgr_csr_aliasing 0.950s 15.692us 0 1 0.00
clkmgr_same_csr_outstanding 1.460s 102.669us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.490s 206.753us 1 1 100.00
clkmgr_tl_intg_err 0.760s 14.283us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.660s 125.468us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.660s 125.468us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.660s 125.468us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.660s 125.468us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 2.440s 239.232us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.760s 14.283us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.850s 6.538us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.790s 12.520us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.660s 125.468us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.040s 50.468us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.490s 206.753us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 35.718us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.490s 206.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.600s 1.858us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.990s 14.645us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 105683773049020093792561764198324726234314761269666465852559798362973962182634 73
UVM_ERROR @ 6538053 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 6538053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 83601578359470740026341928392009019819844266460183778639690568395427777649253 75
UVM_ERROR @ 14644840 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 14644840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 11552981683734960000521190618164451720203581456451261233693539349755516412778 75
UVM_ERROR @ 12519733 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 12519733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 100563942941912757453344326225907855889570416670487940336404164840975981069550 75
UVM_ERROR @ 57805365 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 57805365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 36149810996943933634703353469898408128012014475171381571277183184974151395003 71
UVM_ERROR @ 1857740 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 2 [0x2]) reg name: clkmgr_reg_block.io_meas_ctrl_en
UVM_INFO @ 1857740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 112361659097763257467705142900118002117354451800031678082801723111412514021966 72
UVM_ERROR @ 239232317 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 239232317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 6645956973436787148403578784745756277481405553492630462677324169327898663011 91
UVM_ERROR @ 14282874 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 14282874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 87298975356347649724741696630671006786625225264230584834104405183815672753263 73
UVM_ERROR @ 5897610 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 5897610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 115387219844407552433821919705435958499893476404372728179555856911358582688114 72
UVM_ERROR @ 702438687 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 702438687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_csr_aliasing 92880946679089951467404188873907424723919538460095214096162158552028999781181 73
UVM_ERROR @ 15692138 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 15692138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 34598546645242674763188744271421263238046821424455707068188705581254726851474 73
UVM_ERROR @ 102668970 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe3ed3624 read out mismatch
UVM_INFO @ 102668970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---