Simulation Results: csrng

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.81 %
  • code
  • 92.33 %
  • assert
  • 92.79 %
  • func
  • 78.31 %
  • block
  • 97.01 %
  • line
  • 97.76 %
  • branch
  • 92.49 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 19.112us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 47.447us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 4.000s 17.538us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 551.833us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 32.789us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 38.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 4.000s 17.538us 1 1 100.00
csrng_csr_aliasing 3.000s 32.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
alerts 1 1 100.00
csrng_alert 13.000s 187.891us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 94.000s 5091.024us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 94.000s 5091.024us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 252.000s 16564.721us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 4.000s 105.710us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 16.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 259.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 259.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 47.447us 1 1 100.00
csrng_csr_rw 4.000s 17.538us 1 1 100.00
csrng_csr_aliasing 3.000s 32.789us 1 1 100.00
csrng_same_csr_outstanding 3.000s 109.829us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 47.447us 1 1 100.00
csrng_csr_rw 4.000s 17.538us 1 1 100.00
csrng_csr_aliasing 3.000s 32.789us 1 1 100.00
csrng_same_csr_outstanding 3.000s 109.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 6.000s 157.842us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 4.000s 17.538us 1 1 100.00
csrng_regwen 3.000s 29.603us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 13.000s 187.891us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 252.000s 16564.721us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 13.000s 187.891us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 252.000s 16564.721us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 13.000s 187.891us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 157.842us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
csrng_sec_cm 5.000s 186.601us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 63.423us 1 1 100.00
csrng_err 3.000s 19.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 150.000s 5455.722us 1 1 100.00

Error Messages

   Test seed line log context