Simulation Results: dma

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 91.47 %
  • assert
  • 95.97 %
  • func
  • 62.44 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1261.536us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 623.903us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 619.426us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 13.818us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 19.450us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 296.693us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 173.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 82.757us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 19.450us 1 1 100.00
dma_csr_aliasing 5.000s 173.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 33.000s 2688.968us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 352.000s 48563.769us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 142.000s 27253.687us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 142.000s 27253.687us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 352.000s 48563.769us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 281.000s 21884.814us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 142.000s 27253.687us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 1445.326us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 235.000s 46779.452us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 11.780us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 46.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 88.797us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 88.797us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 13.818us 1 1 100.00
dma_csr_rw 2.000s 19.450us 1 1 100.00
dma_csr_aliasing 5.000s 173.137us 1 1 100.00
dma_same_csr_outstanding 3.000s 67.214us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 13.818us 1 1 100.00
dma_csr_rw 2.000s 19.450us 1 1 100.00
dma_csr_aliasing 5.000s 173.137us 1 1 100.00
dma_same_csr_outstanding 3.000s 67.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 9.000s 514.798us 1 1 100.00
dma_generic_stress 281.000s 21884.814us 1 1 100.00
dma_handshake_stress 142.000s 27253.687us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1425.768us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 112.860us 1 1 100.00
dma_sec_cm 2.000s 26.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 70.000s 4210.939us 1 1 100.00
dma_longer_transfer 4.000s 92.015us 1 1 100.00
dma_stress_all_with_rand_reset 8.000s 510.154us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 96863919566584443578709813888507880588771854354604256181797004462323769475156 92
UVM_ERROR @ 510153589ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 510153589ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---