| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[CFCILFBI] Cannot find cell in liblist | ||||
| default | None | 1714 |
Error-[CFCILFBI] Cannot find cell in liblist
src/lowrisc_dv_edn_sva_0.1/edn_bind.sv, 16
Cell 'edn_csr_assert_fpv' cannot be found in liblist for binding instance
'tb.dut.edn_csr_assert'.
Liblist: work
|
|
| cover_reg_top | None | 1714 |
Error-[CFCILFBI] Cannot find cell in liblist
src/lowrisc_dv_edn_sva_0.1/edn_bind.sv, 16
Cell 'edn_csr_assert_fpv' cannot be found in liblist for binding instance
'tb.dut.edn_csr_assert'.
Liblist: work
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 41921449211112469977251503015065255390249774128563631895632410683875920651550 | None | ||
| edn_tl_intg_err | 57252592628379348929615938822301718338958439656454877464725208317443560099132 | None | ||
| edn_intr_test | 114104760604962905571263641522976537083772219937709895631205381402809478037178 | None | ||
| edn_csr_hw_reset | 59430930311266095762239666126910422875714400552789405621441059587032346603098 | None | ||
| edn_csr_rw | 65541306305065321427604175322466587489631991496772294852474345861121309696179 | None | ||
| edn_csr_bit_bash | 2303957569794807496267729488136508699790371799431177752794584121397022720161 | None | ||
| edn_csr_aliasing | 65137097238661591293698247891930904111228554240878074664730969841092316805246 | None | ||
| edn_same_csr_outstanding | 53274595557011947894294607469811464154084445878895542665239212135789813200404 | None | ||
| edn_csr_mem_rw_with_rand_reset | 18299049226023193249301060218793631791597214914844875407337515712206250192820 | None | ||
| edn_smoke | 70321209976063411753109749283521136459915543504334344971817251775572478583517 | None | ||
| edn_regwen | 52617686196294910937418485937447990866541613128821657339050786415627532685809 | None | ||
| edn_genbits | 92851833738854049385471223423201332262104857190117104354992114428237470257610 | None | ||
| edn_stress_all | 31174609993879066729950756688790082254118992343791804293823795839582579993021 | None | ||
| edn_stress_all_with_rand_reset | 67755882433529126101290985561156875963918156725030926942720691434828166623591 | None | ||
| edn_intr | 111178964418273714504953494025399636542892909877240308955527829802754410554628 | None | ||
| edn_alert | 73892237828101860441613148277875171073314208639764359290755935029980861065865 | None | ||
| edn_err | 40363585439209070651220914228450129137211143773748715296917235904949882271812 | None | ||
| edn_disable | 40188136136568671653567972205166478637784105114618735214894944213288372359920 | None | ||
| edn_disable_auto_req_mode | 44453350387600273277600404753783984584984714885242988620636821011703400050446 | None | ||
| edn_sec_cm | 30631776068298095133748975773383571418446006273152872324315766032482484496881 | None | ||
| edn_alert_test | 84429556205316134196500483331866802270929521229930228131347792072250158944541 | None | ||
| edn | None | None | ||
| edn | None | None | ||