| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
~~~~~~~~~~~~~~~^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
with open(reg_top_path, 'w', encoding='UTF-8') as fout:
~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
Error: CSR assert gen failed:
Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py /nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml" exited with an error code. See stderr for details.
ERROR: Setup failed : Failed to run generator 'csr_assert_gen'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| cover_reg_top | None | None |
~~~~~~~~~~~~~~~^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
with open(reg_top_path, 'w', encoding='UTF-8') as fout:
~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
Error: CSR assert gen failed:
Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml" exited with an error code. See stderr for details.
ERROR: Setup failed : Failed to run generator 'csr_assert_gen'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 12050352046674526122861899099765966178864616044423027161480336463672387867063 | None | ||
| edn_regwen | 72924008129050051750495827267944540137751536062531094839077100144067547765046 | None | ||
| edn_genbits | 48290323239990535792334537510107170286975499986424390022871870367036183101269 | None | ||
| edn_stress_all | 89418219573665359568026296159897993935837688003630143621636481931229995966041 | None | ||
| edn_stress_all_with_rand_reset | 63801096840205224093317207011362319116597718607768433248033982677496203920190 | None | ||
| edn_intr | 490089059290676975845966549687645707260475921560555547894582451660493243539 | None | ||
| edn_alert | 114089656660338741082110663990775651218376717374634790488699864475379545195052 | None | ||
| edn_err | 23169783815040579884361033429576826554137387330298616044102438527675033782313 | None | ||
| edn_disable | 54813029179417970748507000864603783645570093942595802814845941811783968298984 | None | ||
| edn_disable_auto_req_mode | 93070231107514183272165192684383276858297222213475846768785573113803167350249 | None | ||
| edn_sec_cm | 55760530035143869343666291377701002770373970523294375792961108577136433650066 | None | ||
| edn_alert_test | 24997465801806338618601795373352740562196899428559449925853538283297006238800 | None | ||
| edn_tl_errors | 100829880038204850913994741988867524966273461525776946699426672636047652620997 | None | ||
| edn_tl_intg_err | 103683397018404462895797066473663197455636823116627674343946261571484540126647 | None | ||
| edn_intr_test | 10879094563490242654496402614062536698660667779297809037589998814648013270227 | None | ||
| edn_csr_hw_reset | 50618704210292633327768783257192890437357794366468467543743334402661946006565 | None | ||
| edn_csr_rw | 25235785496031678312580771445409317897631432560490578203295316908497646211936 | None | ||
| edn_csr_bit_bash | 32257969523045150551316140946084095140752704628290562245507082111430680599630 | None | ||
| edn_csr_aliasing | 44896331684972675854723489733640319943558856112165227185936993172752852238848 | None | ||
| edn_same_csr_outstanding | 66284062289014753169566281539748459475276628812818093440144463819595899281423 | None | ||
| edn_csr_mem_rw_with_rand_reset | 77477376974472700509351039901772795727911808635163749106742243472064224374133 | None | ||
| edn | None | None | ||
| edn | None | None | ||