Simulation Results: hmac

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.81 %
  • code
  • 98.02 %
  • assert
  • 96.42 %
  • func
  • 44.98 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.520s 278.141us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.720s 67.396us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.810s 224.477us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.260s 2925.828us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.400s 194.247us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.060s 49.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.810s 224.477us 1 1 100.00
hmac_csr_aliasing 2.400s 194.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 8.720s 1358.655us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 12.730s 1111.167us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 229.930s 41922.253us 1 1 100.00
hmac_test_sha384_vectors 307.460s 9881.446us 1 1 100.00
hmac_test_sha512_vectors 18.330s 221.920us 1 1 100.00
hmac_test_hmac256_vectors 5.360s 421.108us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 242.163us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 226.897us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.670s 1284.004us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 787.750s 17594.578us 1 1 100.00
error 1 1 100.00
hmac_error 58.590s 12488.836us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 75.770s 32741.859us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.520s 278.141us 1 1 100.00
hmac_long_msg 8.720s 1358.655us 1 1 100.00
hmac_back_pressure 12.730s 1111.167us 1 1 100.00
hmac_datapath_stress 787.750s 17594.578us 1 1 100.00
hmac_burst_wr 15.670s 1284.004us 1 1 100.00
hmac_stress_all 273.170s 28030.932us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.520s 278.141us 1 1 100.00
hmac_long_msg 8.720s 1358.655us 1 1 100.00
hmac_back_pressure 12.730s 1111.167us 1 1 100.00
hmac_datapath_stress 787.750s 17594.578us 1 1 100.00
hmac_wipe_secret 75.770s 32741.859us 1 1 100.00
hmac_test_sha256_vectors 229.930s 41922.253us 1 1 100.00
hmac_test_sha384_vectors 307.460s 9881.446us 1 1 100.00
hmac_test_sha512_vectors 18.330s 221.920us 1 1 100.00
hmac_test_hmac256_vectors 5.360s 421.108us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 242.163us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 226.897us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.520s 278.141us 1 1 100.00
hmac_long_msg 8.720s 1358.655us 1 1 100.00
hmac_back_pressure 12.730s 1111.167us 1 1 100.00
hmac_datapath_stress 787.750s 17594.578us 1 1 100.00
hmac_burst_wr 15.670s 1284.004us 1 1 100.00
hmac_error 58.590s 12488.836us 1 1 100.00
hmac_wipe_secret 75.770s 32741.859us 1 1 100.00
hmac_test_sha256_vectors 229.930s 41922.253us 1 1 100.00
hmac_test_sha384_vectors 307.460s 9881.446us 1 1 100.00
hmac_test_sha512_vectors 18.330s 221.920us 1 1 100.00
hmac_test_hmac256_vectors 5.360s 421.108us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 242.163us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 226.897us 1 1 100.00
hmac_stress_all 273.170s 28030.932us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 273.170s 28030.932us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 12.981us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.670s 17.038us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.860s 177.323us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.860s 177.323us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.720s 67.396us 1 1 100.00
hmac_csr_rw 0.810s 224.477us 1 1 100.00
hmac_csr_aliasing 2.400s 194.247us 1 1 100.00
hmac_same_csr_outstanding 1.610s 49.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.720s 67.396us 1 1 100.00
hmac_csr_rw 0.810s 224.477us 1 1 100.00
hmac_csr_aliasing 2.400s 194.247us 1 1 100.00
hmac_same_csr_outstanding 1.610s 49.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.790s 861.338us 1 1 100.00
hmac_tl_intg_err 2.280s 173.919us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.280s 173.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.520s 278.141us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.230s 425.634us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 153.660s 3899.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.120s 34.789us 1 1 100.00

Error Messages

   Test seed line log context