i2c Simulation Results

Simulation Results: i2c

08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.33 %

code
81.61 %

assert
96.41 %

func
80.97 %

line
96.45 %

branch
92.41 %

cond
85.12 %

toggle
89.45 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		91.84%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	35.930s	1144.177us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.040s	6005.048us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.700s	30.018us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.720s	57.498us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.010s	68.048us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.100s	39.273us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.960s	467.155us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.720s	57.498us	1	1	100.00
	i2c_csr_aliasing	1.100s	39.273us	1	1	100.00

45/49 passed

91.84 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.810s	42.588us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	282.630s	14601.500us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	33.490s	4168.149us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.910s	43.196us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	74.040s	5300.760us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	57.640s	6746.150us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.010s	182.126us	1	1	100.00
	i2c_host_fifo_fmt_empty	10.810s	335.400us	1	1	100.00
	i2c_host_fifo_reset_rx	4.200s	999.372us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	45.420s	12734.555us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.840s	15213.610us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.820s	268.848us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.990s	889.629us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	140.440s	18616.238us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.630s	2964.158us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	13.130s	2477.085us	1	1	100.00
	i2c_target_intr_smoke	4.640s	3518.846us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.850s	244.411us	1	1	100.00
	i2c_target_fifo_reset_tx	1.070s	225.536us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	429.010s	45321.251us	1	1	100.00
	i2c_target_stress_rd	13.130s	2477.085us	1	1	100.00
	i2c_target_intr_stress_wr	2.520s	2174.340us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.590s	4588.777us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	31.760s	2813.292us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.220s	2526.233us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	5.530s	10815.965us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.310s	1268.935us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.070s	139.201us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	33.490s	4168.149us	1	1	100.00
	i2c_host_perf_precise	23.830s	2576.076us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.840s	15213.610us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.960s	594.758us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.020s	9749.932us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.880s	3751.596us	1	1	100.00
	i2c_target_nack_txstretch	1.310s	350.802us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.690s	1316.133us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.850s	1049.129us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.690s	19.690us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.760s	17.584us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.560s	87.930us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.560s	87.930us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	30.018us	1	1	100.00
	i2c_csr_rw	0.720s	57.498us	1	1	100.00
	i2c_csr_aliasing	1.100s	39.273us	1	1	100.00
	i2c_same_csr_outstanding	1.090s	110.676us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	30.018us	1	1	100.00
	i2c_csr_rw	0.720s	57.498us	1	1	100.00
	i2c_csr_aliasing	1.100s	39.273us	1	1	100.00
	i2c_same_csr_outstanding	1.090s	110.676us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.950s	69.015us	1	1	100.00
	i2c_tl_intg_err	1.210s	273.496us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.210s	273.496us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.390s	1728.297us	1
target_error_intr				1
	i2c_target_unexp_stop	1.100s	197.403us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.910s	50.870us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	71513878467852270817368838351196799441266774282650202298292732982764525397607	91	UVM_ERROR @ 42587879 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 42587879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	25615638495789632720794218771301525785902025308345929552257854678803388132587	127	UVM_ERROR @ 14601500295 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 14601500295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	4655637393770950002937047510010093914511116346409172452683383635600069004051	82	UVM_ERROR @ 50870399 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 50870399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	27242114637278582469477213416782663904415829720864716771944636611176221020907	81	UVM_ERROR @ 889629036 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 889629036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	23020340809006400957383341004735850208264665668972850727305567371377644756480	75	UVM_ERROR @ 197403326 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) UVM_INFO @ 197403326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	65737691101279055002645676661638020897870480046693607118788776806325864380087	76	UVM_FATAL @ 10815964800 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10815964800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	71572110641938446536982471742531734087469410016472776216259373546628477209724	89	UVM_ERROR @ 1728296977 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1728296977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---