Simulation Results: keymgr

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.45 %
  • code
  • 93.29 %
  • assert
  • 97.49 %
  • func
  • 62.57 %
  • line
  • 98.66 %
  • branch
  • 97.67 %
  • cond
  • 93.65 %
  • toggle
  • 92.74 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.420s 522.076us 1 1 100.00
random 1 1 100.00
keymgr_random 4.270s 417.240us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.050s 34.678us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 7.730s 289.881us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.090s 618.522us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.180s 26.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_csr_aliasing 4.090s 618.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 11.390s 576.593us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.700s 43.044us 1 1 100.00
keymgr_sideload_kmac 1.720s 34.219us 1 1 100.00
keymgr_sideload_aes 4.780s 1570.781us 1 1 100.00
keymgr_sideload_otbn 1.920s 92.157us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.990s 61.081us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.380s 39.434us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.320s 617.817us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.290s 220.293us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 84.602us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.670s 59.043us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 17.730s 6930.904us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.040s 24.927us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.020s 74.236us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.800s 77.949us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.800s 77.949us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 34.678us 1 1 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_csr_aliasing 4.090s 618.522us 1 1 100.00
keymgr_same_csr_outstanding 1.930s 189.918us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 34.678us 1 1 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_csr_aliasing 4.090s 618.522us 1 1 100.00
keymgr_same_csr_outstanding 1.930s 189.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 4.060s 170.645us 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 6.120s 371.035us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 6.120s 371.035us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 6.120s 371.035us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 6.120s 371.035us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.160s 237.261us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.060s 170.645us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 6.120s 371.035us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 11.390s 576.593us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_random 4.270s 417.240us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_random 4.270s 417.240us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 16.674us 1 1 100.00
keymgr_random 4.270s 417.240us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.380s 39.434us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 84.602us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 84.602us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.270s 417.240us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.000s 144.716us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.090s 143.260us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.380s 39.434us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.090s 143.260us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.090s 143.260us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.090s 143.260us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.580s 1034.878us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.090s 143.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 26.620s 4510.166us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 46785257004722766715127275852473746549973944183701501646034895587076507169008 2777
UVM_ERROR @ 4510165672 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4510165672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---