Simulation Results: lc_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.45 %
  • code
  • 87.28 %
  • assert
  • 95.99 %
  • func
  • 85.07 %
  • line
  • 97.69 %
  • branch
  • 96.34 %
  • cond
  • 79.10 %
  • toggle
  • 82.34 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
87.50%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.530s 41.740us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 22.813us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.498us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.570s 81.362us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 61.792us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 108.022us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 16.498us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 61.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3.580s 27.762us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.990s 1149.815us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 156.600us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.310s 541.381us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.110s 1517.666us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_prog_failure 2.310s 541.381us 1 1 100.00
lc_ctrl_errors 7.110s 1517.666us 1 1 100.00
lc_ctrl_security_escalation 4.110s 245.206us 1 1 100.00
lc_ctrl_jtag_state_failure 8.400s 1484.324us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.310s 628.122us 1 1 100.00
lc_ctrl_jtag_errors 21.200s 4872.344us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.740s 772.900us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.470s 102.965us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.340s 1768.458us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.810s 247.251us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.200s 111.113us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.150s 479.256us 1 1 100.00
lc_ctrl_jtag_alert_test 0.990s 29.922us 1 1 100.00
lc_ctrl_jtag_smoke 3.040s 242.471us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.390s 552.713us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.310s 628.122us 1 1 100.00
lc_ctrl_jtag_errors 21.200s 4872.344us 1 1 100.00
lc_ctrl_jtag_access 2.720s 413.296us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.660s 3795.164us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.260s 841.383us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.160s 17.499us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 10.010s 547.436us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.780s 18.758us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 270.847us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 270.847us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 22.813us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.498us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 61.792us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 74.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 22.813us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.498us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 61.792us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 74.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.530s 116.456us 1 1 100.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.530s 116.456us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.990s 1149.815us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.040s 28.455us 0 1 0.00
lc_ctrl_sec_cm 5.520s 129.464us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.110s 245.206us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3.580s 27.762us 0 1 0.00
lc_ctrl_jtag_state_post_trans 4.390s 552.713us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.730s 281.099us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.730s 281.099us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.600s 716.083us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.870s 2564.049us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.870s 2564.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.850s 210.489us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 53628535182947426925072711089641785389565492709355122211752425002536911410884 552
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 28454651 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 28454651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 73917855971410534120916860494093255653787418158848368506881058783949848926129 344
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 27761565 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 27761565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 74318879144889692092684590901404466271748873390393489600327566182972167611538 750
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1484323781 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1484323781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 56274645009088968917473702378675973871185128444846821663825612403574275789670 361
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 552712751 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 552712751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 101883070317339304236120123370171788377566184129007777893362035431612348156870 147
UVM_ERROR @ 210488525 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 210488525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---