Simulation Results: lc_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.23 %
  • code
  • 86.98 %
  • assert
  • 95.99 %
  • func
  • 84.71 %
  • line
  • 97.66 %
  • branch
  • 96.22 %
  • cond
  • 79.63 %
  • toggle
  • 82.32 %
  • FSM
  • 79.07 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.790s 59.555us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 21.308us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 18.002us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.900s 155.149us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 34.448us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.090s 13.829us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 18.002us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 34.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.130s 1.566us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.690s 524.143us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 90.120us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.130s 219.919us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.890s 442.702us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_prog_failure 2.130s 219.919us 1 1 100.00
lc_ctrl_errors 10.890s 442.702us 1 1 100.00
lc_ctrl_security_escalation 8.090s 676.832us 1 1 100.00
lc_ctrl_jtag_state_failure 5.690s 1037.664us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.240s 457.187us 1 1 100.00
lc_ctrl_jtag_errors 70.000s 4186.689us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.550s 88.896us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.580s 167.947us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 40.000s 33476.859us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.830s 1359.686us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.090s 140.944us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.460s 182.974us 1 1 100.00
lc_ctrl_jtag_alert_test 1.650s 160.910us 1 1 100.00
lc_ctrl_jtag_smoke 2.060s 556.070us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.860s 107.841us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.240s 457.187us 1 1 100.00
lc_ctrl_jtag_errors 70.000s 4186.689us 1 1 100.00
lc_ctrl_jtag_access 4.860s 651.910us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.130s 1302.522us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.090s 3687.641us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 48.473us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 31.640s 6709.148us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 94.111us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.290s 552.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.290s 552.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 21.308us 1 1 100.00
lc_ctrl_csr_rw 0.930s 18.002us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 34.448us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.350s 83.344us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 21.308us 1 1 100.00
lc_ctrl_csr_rw 0.930s 18.002us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 34.448us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.350s 83.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.720s 114.110us 1 1 100.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 114.110us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.690s 524.143us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.240s 30.125us 0 1 0.00
lc_ctrl_sec_cm 5.920s 228.303us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.090s 676.832us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.130s 1.566us 0 1 0.00
lc_ctrl_jtag_state_post_trans 5.860s 107.841us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 346.062us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 346.062us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.300s 621.181us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.020s 1969.881us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.020s 1969.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.310s 3686.134us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 58194577881939886427584494539752177559179567588505521581786001211501915539504 563
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 30125382 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 30125382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 109402070342645944842713836825165556438783845077349546576045907184170681898547 121
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1566343 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1566343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 52768567822368357780959188925908125985325438740093450038941645705473154017705 796
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1037664327 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1037664327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 21517683198677490180868625554421669594307959871401092502528565497126198120440 281
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 107841296 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 107841296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 110361436752858977488050101164922078972437697096500828936432262357145223001043 7510
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 6709147723 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 6709147723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22793211455887454640902856453388148835669987882335161753404138985090295192563 4217
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3686134427 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3686134427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---