Simulation Results: mbx

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.40 %
  • code
  • 90.00 %
  • assert
  • 97.01 %
  • func
  • 84.18 %
  • block
  • 95.26 %
  • line
  • 95.84 %
  • branch
  • 88.11 %
  • toggle
  • 86.04 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 46.000s 7897.869us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 15.468us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 67.871us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 155.566us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 51.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 46.605us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 67.871us 1 1 100.00
mbx_csr_aliasing 2.000s 51.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 63.000s 21756.328us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 5.000s 15.949us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 7.000s 354.606us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 22.000s 541.383us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 5.000s 170.843us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 54.088us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
mbx_tl_errors 3.000s 350.674us 1 1 100.00
tl_d_illegal_access 1 1 100.00
mbx_tl_errors 3.000s 350.674us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.468us 1 1 100.00
mbx_csr_rw 2.000s 67.871us 1 1 100.00
mbx_csr_aliasing 2.000s 51.386us 1 1 100.00
mbx_same_csr_outstanding 2.000s 110.888us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.468us 1 1 100.00
mbx_csr_rw 2.000s 67.871us 1 1 100.00
mbx_csr_aliasing 2.000s 51.386us 1 1 100.00
mbx_same_csr_outstanding 2.000s 110.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 4.000s 34.298us 1 1 100.00
mbx_tl_intg_err 1.000s 269.939us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress_zero_delays 8824297708240460427286618800155308930615870610066783508736009543114594698937 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 15949179 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 15949179 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 15949179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_imbx_oob 92563922004953568100781785853372810183848249776103850759659932842755615099612 91
UVM_ERROR @ 354606426 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 354606426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---