Simulation Results: otp_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.85 %
  • code
  • 70.05 %
  • assert
  • 92.43 %
  • func
  • 50.07 %
  • line
  • 87.46 %
  • branch
  • 83.71 %
  • cond
  • 85.34 %
  • toggle
  • 55.80 %
  • FSM
  • 37.95 %
Validation stages
V1
90.91%
V2
76.00%
V2S
76.79%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.070s 84.359us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.590s 1830.301us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.700s 60.076us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.600s 1097.990us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.670s 253.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 5.180s 1912.056us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.700s 60.076us 1 1 100.00
otp_ctrl_csr_aliasing 6.670s 253.345us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.130s 81.673us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.440s 44.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 100.820s 19980.923us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.500s 257.478us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 11.650s 2606.844us 0 1 0.00
otp_ctrl_check_fail 3.140s 941.652us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.660s 132.891us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 12.450s 1049.502us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.050s 532.619us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 25.470s 1327.808us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 14.250s 2083.823us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 4.150s 610.611us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 9.710s 397.077us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.540s 160.003us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.010s 80.427us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.860s 1159.594us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.860s 1159.594us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.590s 1830.301us 1 1 100.00
otp_ctrl_csr_rw 1.700s 60.076us 1 1 100.00
otp_ctrl_csr_aliasing 6.670s 253.345us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.960s 204.139us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.590s 1830.301us 1 1 100.00
otp_ctrl_csr_rw 1.700s 60.076us 1 1 100.00
otp_ctrl_csr_aliasing 6.670s 253.345us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.960s 204.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 13.300s 2750.747us 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.300s 2750.747us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_macro_errs 14.250s 2083.823us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_macro_errs 14.250s 2083.823us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.840s 122.469us 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.500s 257.478us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.140s 941.652us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 10.510s 4749.729us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 274.530s 41974.913us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.660s 132.891us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 7.500s 453.583us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 14.250s 2083.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 115.880s 46175.727us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.850s 498.284us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_smoke 24339002593713752292465196234614045935084788810293373678786721672332691990139 8969
UVM_ERROR @ 453582799 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 453582799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 59272323827759159010138441207917082872011239549903556405972157650261390730629 115558
UVM_ERROR @ 19980922748 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 19980922748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 75964177777051111688923948916722274301499692160982637759698052083972830837524 86
UVM_ERROR @ 46175727238 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 46175727238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 49994117666330796193344409464131192178185521616748185696905814355076155312376 6329
UVM_ERROR @ 2606843509 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2606843509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_dai_lock 86319216453531877189160963765051713323703578742515351465194951993242998304356 5696
UVM_ERROR @ 4749728901 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 4749728901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86654026917440997983915134092000855695635206592121723428138547703338668880324 2281
UVM_ERROR @ 941652049 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 941652049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 83532838606649848102238394792098709568759997895551386366823653426579999708241 10364
UVM_ERROR @ 397077239 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 397077239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_parallel_key_req 85165353059111251907190131348895391796371034093647944469730729838359712194900 17557
UVM_ERROR @ 1049501588 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1049501588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 3193758015756853888334896762186805225947480609970679749261841170126223672443 91
UVM_ERROR @ 498284156 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 498284156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---