Simulation Results: rom_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 98.36 %
  • assert
  • 95.49 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 94.21 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.470s 430.073us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.840s 879.296us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.140s 169.958us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.500s 538.411us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 214.475us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.790s 555.502us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.140s 169.958us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 214.475us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.390s 128.560us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.560s 535.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.840s 457.507us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.560s 667.734us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.510s 571.525us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.060s 628.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.990s 129.554us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.990s 129.554us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.840s 879.296us 1 1 100.00
rom_ctrl_csr_rw 4.140s 169.958us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 214.475us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.280s 545.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.840s 879.296us 1 1 100.00
rom_ctrl_csr_rw 4.140s 169.958us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 214.475us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.280s 545.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.320s 1094.747us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
rom_ctrl_tl_intg_err 42.250s 1188.905us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.470s 430.073us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.470s 430.073us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.470s 430.073us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.250s 1188.905us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
rom_ctrl_kmac_err_chk 8.510s 571.525us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.560s 4327.736us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.320s 1094.747us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 193.470s 997.481us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 146.510s 8299.394us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 33113712888944715386038196244803840035309077698640934414268300884101247476675 292
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 23757053ps failed at 23757053ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 23777886ps failed at 23777886ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'