Simulation Results: rom_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.16 %
  • code
  • 95.71 %
  • assert
  • 95.34 %
  • func
  • 85.44 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 94.65 %
  • toggle
  • 99.57 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.020s 550.211us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.960s 1077.115us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.590s 1113.894us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.320s 1339.133us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 506.916us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.780s 760.220us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.590s 1113.894us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 506.916us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.560s 296.101us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.360s 607.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 10.110s 4014.768us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.700s 583.784us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.240s 381.526us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.510s 289.718us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 13.670s 299.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 13.670s 299.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.960s 1077.115us 1 1 100.00
rom_ctrl_csr_rw 6.590s 1113.894us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 506.916us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.460s 536.872us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.960s 1077.115us 1 1 100.00
rom_ctrl_csr_rw 6.590s 1113.894us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 506.916us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.460s 536.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.320s 2769.053us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
rom_ctrl_tl_intg_err 94.130s 740.205us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.020s 550.211us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.020s 550.211us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.020s 550.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.130s 740.205us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
rom_ctrl_kmac_err_chk 13.240s 381.526us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.940s 10821.268us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.320s 2769.053us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 452.630s 2099.483us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 115.740s 7496.376us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 34503037175333747747658192506925074780346016094223242242729892501785423950140 165
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26753452ps failed at 26753452ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26773452ps failed at 26773452ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'