Simulation Results: rstmgr

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.05 %
  • code
  • 99.43 %
  • assert
  • 97.44 %
  • func
  • 94.28 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.20 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.130s 65.595us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.910s 65.353us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.410s 142.999us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.190s 49.961us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.420s 96.808us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00
rstmgr_csr_aliasing 1.190s 49.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.050s 113.117us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.930s 38.349us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.840s 61.277us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.940s 563.498us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.940s 563.498us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.940s 563.498us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.940s 563.498us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 2.120s 231.263us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 50.484us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.950s 76.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.950s 76.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 65.353us 1 1 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00
rstmgr_csr_aliasing 1.190s 49.961us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 37.114us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 65.353us 1 1 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00
rstmgr_csr_aliasing 1.190s 49.961us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 37.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.680s 3434.397us 1 1 100.00
rstmgr_tl_intg_err 3.660s 623.504us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.680s 3434.397us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.680s 3434.397us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.660s 623.504us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.900s 57.917us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.110s 421.606us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.810s 291.896us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.680s 3434.397us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 35.746us 1 1 100.00

Error Messages

   Test seed line log context