Simulation Results: rv_timer

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.76 %
  • code
  • 99.92 %
  • assert
  • 96.82 %
  • func
  • 93.53 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.700s 82.892us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.770s 38.673us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.730s 16.995us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.110s 130.004us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.940s 26.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.090s 91.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.730s 16.995us 1 1 100.00
rv_timer_csr_aliasing 0.940s 26.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.840s 955.958us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.960s 3053.656us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 169.100s 147456.864us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 169.100s 147456.864us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 7.060s 8230.098us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.580s 31.884us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.810s 14.743us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.280s 204.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.280s 204.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 38.673us 1 1 100.00
rv_timer_csr_rw 0.730s 16.995us 1 1 100.00
rv_timer_csr_aliasing 0.940s 26.957us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 161.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 38.673us 1 1 100.00
rv_timer_csr_rw 0.730s 16.995us 1 1 100.00
rv_timer_csr_aliasing 0.940s 26.957us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 161.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_tl_intg_err 1.050s 1065.036us 1 1 100.00
rv_timer_sec_cm 0.910s 200.245us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.050s 1065.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.780s 347.689us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.730s 48.982us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.690s 11333.012us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 100531146042032113503823463638602347175352623413457803432396260024936869963421 74
UVM_FATAL @ 347688719 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3794ed04) == 0x1
UVM_INFO @ 347688719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 28245773485632523872691941458139408299821159590771313907815464996110811737691 72
UVM_FATAL @ 955958200 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x38a99704) == 0x1
UVM_INFO @ 955958200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 82872652568870056144963448766894847292791948353677559731242957666336558416195 73
UVM_ERROR @ 48981711 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 48981711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---