spi_device Simulation Results

Simulation Results: spi_device

08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.85 %

code
93.19 %

assert
94.30 %

func
67.06 %

line
99.02 %

branch
98.18 %

cond
95.86 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		96.15%
V2S		100.00%
unmapped		100.00%

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	50.030s	38513.707us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.270s	33.562us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	2.340s	450.786us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	23.770s	7550.681us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	14.080s	854.706us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	3.700s	528.278us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	2.340s	450.786us	1	1	100.00
	spi_device_csr_aliasing	14.080s	854.706us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.820s	13.751us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.310s	35.007us	1	1	100.00

50/52 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.770s	256.137us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.690s	2.703us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.720s	3.063us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	1.020s	20.981us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	1.020s	20.981us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	0.890s	240.005us	1	1	100.00
	spi_device_tpm_sts_read	0.790s	56.492us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	7.470s	926.634us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	1.910s	51.255us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.000s	147.750us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.000s	147.750us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	2.100s	98.003us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	2.100s	98.003us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	2.100s	98.003us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	2.100s	98.003us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	2.100s	98.003us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	1.620s	119.635us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	50.240s	9605.874us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	50.240s	9605.874us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	50.240s	9605.874us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	27.490s	5627.887us	1	1	100.00
	spi_device_read_buffer_direct	5.750s	2972.453us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	50.240s	9605.874us	1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	21.990s	1414.608us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	4.250s	417.189us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	4.250s	417.189us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	50.030s	38513.707us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	160.690s	24874.648us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	1.350s	399.646us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.800s	39.785us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.710s	31.825us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	2.240s	1014.790us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	2.240s	1014.790us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.270s	33.562us	1	1	100.00
	spi_device_csr_rw	2.340s	450.786us	1	1	100.00
	spi_device_csr_aliasing	14.080s	854.706us	1	1	100.00
	spi_device_same_csr_outstanding	2.900s	48.145us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.270s	33.562us	1	1	100.00
	spi_device_csr_rw	2.340s	450.786us	1	1	100.00
	spi_device_csr_aliasing	14.080s	854.706us	1	1	100.00
	spi_device_same_csr_outstanding	2.900s	48.145us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	11.320s	7297.994us	1	1	100.00
	spi_device_sec_cm	1.270s	389.452us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	11.320s	7297.994us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	216.160s	71263.790us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	51419381411965401463275292505897363981954718147186335456778273482550512732228	73	UVM_ERROR @ 2335172 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[37]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 2335172 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 2335172 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	24105787902501055031552880651540845409720895467006171690268426542372669220947	73	UVM_ERROR @ 696909 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdd8794 [110111011000011110010100] vs 0x0 [0]) UVM_ERROR @ 784909 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x32afa7 [1100101010111110100111] vs 0x0 [0]) UVM_ERROR @ 812909 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4310bc [10000110001000010111100] vs 0x0 [0]) UVM_ERROR @ 912909 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4b6708 [10010110110011100001000] vs 0x0 [0]) UVM_ERROR @ 995909 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfaa7ef [111110101010011111101111] vs 0x0 [0])