Simulation Results: sram_ctrl

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 95.90 %
  • assert
  • 95.79 %
  • func
  • 95.18 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.29 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.460s 596.732us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.960s 57.046us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.860s 16.287us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.910s 686.359us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 23.323us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.040s 128.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.860s 16.287us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 23.323us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.600s 294.437us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.450s 330.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 1202.890s 10343.278us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 199.610s 11063.283us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 20.990s 2672.319us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 540.710s 3392.611us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.340s 334.890us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.890s 250.988us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 10.820s 1177.075us 1 1 100.00
sram_ctrl_partial_access_b2b 190.680s 40345.190us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 53.390s 160.289us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.320s 65.824us 1 1 100.00
sram_ctrl_throughput_w_readback 53.040s 569.705us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 412.020s 21634.400us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.960s 29.619us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 827.230s 116604.384us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.950s 12.472us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.360s 1070.654us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.360s 1070.654us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.960s 57.046us 1 1 100.00
sram_ctrl_csr_rw 0.860s 16.287us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 23.323us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 26.484us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.960s 57.046us 1 1 100.00
sram_ctrl_csr_rw 0.860s 16.287us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 23.323us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 26.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.180s 402.502us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
sram_ctrl_tl_intg_err 2.210s 327.715us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.210s 327.715us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 412.020s 21634.400us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 412.020s 21634.400us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.860s 16.287us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.890s 250.988us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.890s 250.988us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.890s 250.988us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.340s 334.890us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.940s 41.537us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.180s 402.502us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.210s 43.956us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.460s 596.732us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.460s 596.732us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.890s 250.988us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.340s 334.890us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.460s 596.732us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.930s 1.782us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.000s 1216.772us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 99508740826558530586570261117265781222179306743206007312234648164944083955793 97
UVM_ERROR @ 1781863 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1781863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---