Simulation Results: uart

 
08/12/2025 16:09:22 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.93 %
  • code
  • 95.35 %
  • assert
  • 97.12 %
  • func
  • 50.31 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 93.47 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.310s 639.554us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.770s 25.758us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 12.280us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.260s 360.451us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.770s 118.539us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.820s 69.668us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 12.280us 1 1 100.00
uart_csr_aliasing 0.770s 118.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 120.470s 109166.067us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.310s 639.554us 1 1 100.00
uart_tx_rx 120.470s 109166.067us 1 1 100.00
parity_error 2 2 100.00
uart_intr 1.500s 3134.720us 1 1 100.00
uart_rx_parity_err 19.070s 21503.102us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 120.470s 109166.067us 1 1 100.00
uart_intr 1.500s 3134.720us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 14.270s 17342.107us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 13.920s 39051.339us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 14.760s 97098.541us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 1.500s 3134.720us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 1.500s 3134.720us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 1.500s 3134.720us 1 1 100.00
perf 1 1 100.00
uart_perf 93.970s 13179.588us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.790s 3895.629us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.790s 3895.629us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 53.320s 46403.595us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.600s 2945.930us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.400s 1146.732us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 31.460s 5631.206us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 307.880s 82903.476us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 116.100s 104007.272us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.670s 16.179us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 11.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.030s 37.382us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.030s 37.382us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.770s 25.758us 1 1 100.00
uart_csr_rw 0.620s 12.280us 1 1 100.00
uart_csr_aliasing 0.770s 118.539us 1 1 100.00
uart_same_csr_outstanding 0.740s 35.392us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.770s 25.758us 1 1 100.00
uart_csr_rw 0.620s 12.280us 1 1 100.00
uart_csr_aliasing 0.770s 118.539us 1 1 100.00
uart_same_csr_outstanding 0.740s 35.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.920s 65.439us 1 1 100.00
uart_tl_intg_err 1.020s 272.015us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.020s 272.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 50.410s 4513.324us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 27616099367003713401923051306529535395762509673773604718646530948180314786077 74
UVM_ERROR @ 45799648998 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 45799659415 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 45799669832 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12 [0xc] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 45898506328 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 45898516745 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr
uart_stress_all_with_rand_reset 89858331365328883318256218151508193198238771715709325293705013025374352872432 180
UVM_ERROR @ 3147269556 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 3147269556 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 3153363501 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/742
UVM_INFO @ 3250564528 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/742
UVM_ERROR @ 3263023260 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0