| V1 |
|
100.00% |
| V2 |
|
94.44% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 4.450s | 45.999us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 42.080s | 248.319us | 1 | 1 | 100.00 | |
| xbar_random_delay | 5 | 6 | 83.33 | |||
| xbar_smoke_zero_delays | 4.300s | 54.315us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 200.630s | 36879.993us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 206.690s | 32465.600us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 17.720s | 303.548us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 888.400s | 600000.000us | 0 | 1 | 0.00 | |
| xbar_random_slow_rsp | 207.360s | 52178.006us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 9.410s | 552.271us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 57.410s | 2412.957us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 46.020s | 2485.691us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 57.410s | 2412.957us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 19.380s | 126.205us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1564.390s | 360707.733us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 39.170s | 8796.831us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 600.520s | 126901.186us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 174.760s | 2311.515us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 485.120s | 1498.255us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 14.860s | 66.164us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| xbar_random_large_delays | 45540281101458988840456046126686010395973283158697557406269701552372332763087 | 148 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|