Simulation Results: aes

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.91 %
  • code
  • 92.15 %
  • assert
  • 97.69 %
  • func
  • 79.88 %
  • block
  • 93.90 %
  • line
  • 95.11 %
  • branch
  • 88.83 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 200.832us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 87.310us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.007us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 55.021us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1551.672us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 297.503us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 112.627us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 55.021us 1 1 100.00
aes_csr_aliasing 2.000s 297.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 87.310us 1 1 100.00
aes_config_error 3.000s 77.120us 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 87.310us 1 1 100.00
aes_config_error 3.000s 77.120us 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 112.156us 1 1 100.00
aes_b2b 5.000s 360.001us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 87.310us 1 1 100.00
aes_config_error 3.000s 77.120us 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 55.265us 1 1 100.00
aes_config_error 3.000s 77.120us 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 108.395us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 324.740us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 112.156us 1 1 100.00
aes_sideload 3.000s 89.927us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 167.170us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 14.000s 2319.864us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 61.549us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 120.421us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 120.421us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.007us 1 1 100.00
aes_csr_rw 1.000s 55.021us 1 1 100.00
aes_csr_aliasing 2.000s 297.503us 1 1 100.00
aes_same_csr_outstanding 3.000s 294.930us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.007us 1 1 100.00
aes_csr_rw 1.000s 55.021us 1 1 100.00
aes_csr_aliasing 2.000s 297.503us 1 1 100.00
aes_same_csr_outstanding 3.000s 294.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 204.210us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 143.926us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 106.305us 1 1 100.00
aes_sec_cm 3.000s 1206.486us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 106.305us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 87.310us 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
aes_core_fi 2.000s 61.681us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 232.378us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 89.167us 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 112.156us 1 1 100.00
aes_sideload 3.000s 89.927us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 89.167us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 89.167us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 89.167us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 89.167us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 89.167us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 112.156us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 81.521us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 81.521us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 81.521us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 368.850us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_ctr_fi 2.000s 59.943us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 81.521us 1 1 100.00
aes_control_fi 2.000s 61.014us 1 1 100.00
aes_cipher_fi 2.000s 49.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 31.000s 1048.031us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 11285013989037396801499702301808182196457980427786374986549001014192929675764 404
UVM_ERROR @ 1048031052 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1048031052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---