Simulation Results: dma

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 91.82 %
  • assert
  • 95.97 %
  • func
  • 61.05 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 289.928us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 503.720us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 958.493us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 31.592us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 18.417us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 1038.455us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 618.900us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 72.514us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 18.417us 1 1 100.00
dma_csr_aliasing 6.000s 618.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 52.000s 5131.178us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 179.000s 28519.262us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 136.000s 42440.848us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 136.000s 42440.848us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 179.000s 28519.262us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 476.000s 352344.117us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 136.000s 42440.848us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 3.000s 110.010us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 292.000s 88668.089us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 13.252us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 37.199us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 407.301us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 407.301us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 31.592us 1 1 100.00
dma_csr_rw 1.000s 18.417us 1 1 100.00
dma_csr_aliasing 6.000s 618.900us 1 1 100.00
dma_same_csr_outstanding 2.000s 1282.918us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 31.592us 1 1 100.00
dma_csr_rw 1.000s 18.417us 1 1 100.00
dma_csr_aliasing 6.000s 618.900us 1 1 100.00
dma_same_csr_outstanding 2.000s 1282.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 17.000s 92.137us 1 1 100.00
dma_generic_stress 476.000s 352344.117us 1 1 100.00
dma_handshake_stress 136.000s 42440.848us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 294.573us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 192.771us 1 1 100.00
dma_sec_cm 1.000s 30.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 46.000s 11107.300us 1 1 100.00
dma_longer_transfer 3.000s 372.534us 1 1 100.00
dma_stress_all_with_rand_reset 17.000s 5477.832us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 51358150412773481065696230950714270618674863080670817219997345322291218225357 114
UVM_ERROR @ 5477831873ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5477831873ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---