| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[P1ARGS-CANTOPN-F] Cannot open file | ||||
| default | None | 41 |
Error-[P1ARGS-CANTOPN-F] Cannot open file
Unable to open
'/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/lowrisc_dv_edn_sim_0.1.scr'
due to 'No such file or directory'.
Please fix the reason mentioned above and continue.
|
|
| Error-[SFCOR] Source file cannot be opened | ||||
| cover_reg_top | None | 375 |
Error-[SFCOR] Source file cannot be opened
Source file "src/lowrisc_dv_pins_if_0/pins_if.sv" cannot be opened for
reading due to 'No such file or directory'.
Please fix above issue and compile again.
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 49569514508525601194381334535191298190684144215957987756212502822456283120975 | None | ||
| edn_regwen | 84299493314796196498087227973840932917863418548254907487814649815550626431595 | None | ||
| edn_genbits | 60885847558277727188458267717329786452448938696496250628728092602931754796942 | None | ||
| edn_stress_all | 79156632727627064787690524380925136446879310562087675146902917853225461041847 | None | ||
| edn_stress_all_with_rand_reset | 89115880830353340556910697812289173807643019627336361447150476484356943663215 | None | ||
| edn_intr | 23260819756652439544471679174678387344930245794872182589922980069230280009109 | None | ||
| edn_alert | 99011058182940848675351462165515535523381732936557675400135365494660969342333 | None | ||
| edn_err | 83478438505918243595113574077022296575341407282373881525087006069227712639921 | None | ||
| edn_disable | 51240030153374425691032559250299999106193918990132835685918357925536501839780 | None | ||
| edn_disable_auto_req_mode | 47850587747894188277130320252933949748954185091211174488389437499828140003005 | None | ||
| edn_sec_cm | 79538221725939335048047642504128155719266746311879683256875423450409017441249 | None | ||
| edn_alert_test | 105885061315088038258399758166955824992645808351635929994037930480536380239125 | None | ||
| edn_tl_errors | 85739454321954018708000271227092729908879027793679445349447248047257833980788 | None | ||
| edn_tl_intg_err | 29120722149647560801954436069429207291097308052572660280443996465653110615668 | None | ||
| edn_intr_test | 17234091942260507113407886740128630240745168962880544916059080108883141410063 | None | ||
| edn_csr_hw_reset | 48341046998943072033779449414781075362573686143939556428740096707759695985028 | None | ||
| edn_csr_rw | 49719432923464701638303520881108451664869893087982243851813936870942387797609 | None | ||
| edn_csr_bit_bash | 102764905455651091451363454164755843020686567220716059598326182725250853791327 | None | ||
| edn_csr_aliasing | 13173275918059389916334783036947845144834696129141528592953643319553195210930 | None | ||
| edn_same_csr_outstanding | 90061593242081546885754385986802966867246199384456022944244465815630333900480 | None | ||
| edn_csr_mem_rw_with_rand_reset | 34674509042335555357291616333284072804889977103689785244936317461867848449474 | None | ||
| edn | None | None | ||
| edn | None | None | ||