| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[P1ARGS-CANTOPN-F] Cannot open file | ||||
| default | None | 41 |
Error-[P1ARGS-CANTOPN-F] Cannot open file
Unable to open
'/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/lowrisc_dv_edn_sim_0.1.scr'
due to 'No such file or directory'.
Please fix the reason mentioned above and continue.
|
|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
_rmtree_safe_fd(stack, onexc)
~~~~~~~~~~~~~~~^^^^^^^^^^^^^^
File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/shutil.py", line 707, in _rmtree_safe_fd
onexc(func, path, err)
~~~~~^^^^^^^^^^^^^^^^^
File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/shutil.py", line 658, in _rmtree_safe_fd
os.rmdir(name, dir_fd=dirfd)
~~~~~~~~^^^^^^^^^^^^^^^^^^^^
OSError: [Errno 39] Directory not empty: '/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/src'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 105719293762422561671390776417034563435428456214047747726162328492785951485490 | None | ||
| edn_tl_intg_err | 101892857743925220269408989475877402838654778684792207244122115966782331343073 | None | ||
| edn_intr_test | 61349404276376522419852002702827826311374811091228851020263657931732002765794 | None | ||
| edn_csr_hw_reset | 73200972602677928899401204335543863228754208800974681975231636420797749506508 | None | ||
| edn_csr_rw | 98644632773773481630219989790957548749466591632816683994143026696754451673417 | None | ||
| edn_csr_bit_bash | 30506210329701274214838618110467508953544356889792152690205021056504085067526 | None | ||
| edn_csr_aliasing | 26036457253096026318293960366346811663561653704234466608083229980132337016486 | None | ||
| edn_same_csr_outstanding | 56122906411510933129966557129116975704855013744847815600445875460828730739055 | None | ||
| edn_csr_mem_rw_with_rand_reset | 52370772689838558660121642293679082833325176629368690246272121291877588613445 | None | ||
| edn_smoke | 71427856990649193285022215184146375534291588671373348103268248205888765792508 | None | ||
| edn_regwen | 63839126594771655606618748299742463809131267673486286376005106870317517444981 | None | ||
| edn_genbits | 96251943301284104668116529850303709207406739155072611763487563965788545251125 | None | ||
| edn_stress_all | 108133298473445897304722336969179243987894699957987660982269507353237013190406 | None | ||
| edn_stress_all_with_rand_reset | 107760324938524124859465174622642772848474374673593431451344456285362664933164 | None | ||
| edn_intr | 43825409633464565957251951263958012539377550142991852135405955539516721475987 | None | ||
| edn_alert | 57541095110968814987798856767044123783717539368730163950712334359376670589553 | None | ||
| edn_err | 85010630102831520474486923492739891014597131172761144524229878367841750997962 | None | ||
| edn_disable | 11586082293752244974105461830199347458164113622123532949274380842387693966582 | None | ||
| edn_disable_auto_req_mode | 24494412428363206017571893462028990244826673311033930053965542965822684659904 | None | ||
| edn_sec_cm | 80179827361609704207185761648335834642347080774727066020614379693981142370385 | None | ||
| edn_alert_test | 49103012146278993546637018585130642369197830896370423476891634961469955062725 | None | ||
| edn | None | None | ||
| edn | None | None | ||