Simulation Results: hmac

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.17 %
  • code
  • 97.61 %
  • assert
  • 96.42 %
  • func
  • 43.48 %
  • line
  • 99.63 %
  • branch
  • 98.68 %
  • cond
  • 95.62 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.480s 253.841us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 38.888us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.840s 49.699us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.580s 1052.435us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.120s 1299.136us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.130s 100.396us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.840s 49.699us 1 1 100.00
hmac_csr_aliasing 4.120s 1299.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 61.180s 2841.508us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 19.100s 2164.727us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.980s 174.770us 1 1 100.00
hmac_test_sha384_vectors 20.150s 911.795us 1 1 100.00
hmac_test_sha512_vectors 413.230s 54019.728us 1 1 100.00
hmac_test_hmac256_vectors 6.300s 218.484us 1 1 100.00
hmac_test_hmac384_vectors 6.670s 207.409us 1 1 100.00
hmac_test_hmac512_vectors 7.410s 215.461us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.480s 2861.935us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 863.760s 5947.685us 1 1 100.00
error 1 1 100.00
hmac_error 3.310s 466.317us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 85.560s 6516.717us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.480s 253.841us 1 1 100.00
hmac_long_msg 61.180s 2841.508us 1 1 100.00
hmac_back_pressure 19.100s 2164.727us 1 1 100.00
hmac_datapath_stress 863.760s 5947.685us 1 1 100.00
hmac_burst_wr 13.480s 2861.935us 1 1 100.00
hmac_stress_all 74.550s 16575.450us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.480s 253.841us 1 1 100.00
hmac_long_msg 61.180s 2841.508us 1 1 100.00
hmac_back_pressure 19.100s 2164.727us 1 1 100.00
hmac_datapath_stress 863.760s 5947.685us 1 1 100.00
hmac_wipe_secret 85.560s 6516.717us 1 1 100.00
hmac_test_sha256_vectors 8.980s 174.770us 1 1 100.00
hmac_test_sha384_vectors 20.150s 911.795us 1 1 100.00
hmac_test_sha512_vectors 413.230s 54019.728us 1 1 100.00
hmac_test_hmac256_vectors 6.300s 218.484us 1 1 100.00
hmac_test_hmac384_vectors 6.670s 207.409us 1 1 100.00
hmac_test_hmac512_vectors 7.410s 215.461us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.480s 253.841us 1 1 100.00
hmac_long_msg 61.180s 2841.508us 1 1 100.00
hmac_back_pressure 19.100s 2164.727us 1 1 100.00
hmac_datapath_stress 863.760s 5947.685us 1 1 100.00
hmac_burst_wr 13.480s 2861.935us 1 1 100.00
hmac_error 3.310s 466.317us 1 1 100.00
hmac_wipe_secret 85.560s 6516.717us 1 1 100.00
hmac_test_sha256_vectors 8.980s 174.770us 1 1 100.00
hmac_test_sha384_vectors 20.150s 911.795us 1 1 100.00
hmac_test_sha512_vectors 413.230s 54019.728us 1 1 100.00
hmac_test_hmac256_vectors 6.300s 218.484us 1 1 100.00
hmac_test_hmac384_vectors 6.670s 207.409us 1 1 100.00
hmac_test_hmac512_vectors 7.410s 215.461us 1 1 100.00
hmac_stress_all 74.550s 16575.450us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 74.550s 16575.450us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.560s 16.519us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.560s 12.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.920s 124.605us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.920s 124.605us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 38.888us 1 1 100.00
hmac_csr_rw 0.840s 49.699us 1 1 100.00
hmac_csr_aliasing 4.120s 1299.136us 1 1 100.00
hmac_same_csr_outstanding 1.860s 114.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 38.888us 1 1 100.00
hmac_csr_rw 0.840s 49.699us 1 1 100.00
hmac_csr_aliasing 4.120s 1299.136us 1 1 100.00
hmac_same_csr_outstanding 1.860s 114.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.980s 62.079us 1 1 100.00
hmac_tl_intg_err 1.460s 95.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.460s 95.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.480s 253.841us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.360s 64.378us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 107.890s 4247.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.090s 1812.187us 1 1 100.00

Error Messages

   Test seed line log context