Simulation Results: i2c

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.51 %
  • code
  • 81.41 %
  • assert
  • 96.19 %
  • func
  • 81.92 %
  • line
  • 96.38 %
  • branch
  • 92.26 %
  • cond
  • 84.89 %
  • toggle
  • 89.45 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 14.420s 3242.947us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 20.860s 3250.723us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.710s 86.335us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.840s 26.920us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.830s 1088.328us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.740s 118.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.310s 26.074us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.840s 26.920us 1 1 100.00
i2c_csr_aliasing 1.740s 118.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.530s 82.179us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 685.430s 96896.367us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 1572.210s 28865.779us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.660s 17.044us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 60.320s 7769.452us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 68.870s 1731.513us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.800s 300.582us 1 1 100.00
i2c_host_fifo_fmt_empty 7.380s 425.074us 1 1 100.00
i2c_host_fifo_reset_rx 4.340s 1043.887us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 71.940s 11350.154us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 15.220s 1703.998us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.830s 15.054us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.730s 1805.849us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 34.620s 10505.731us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.260s 2702.027us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 15.790s 7143.377us 1 1 100.00
i2c_target_intr_smoke 6.440s 6287.629us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.050s 357.500us 1 1 100.00
i2c_target_fifo_reset_tx 1.490s 812.908us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 206.690s 35827.447us 1 1 100.00
i2c_target_stress_rd 15.790s 7143.377us 1 1 100.00
i2c_target_intr_stress_wr 16.300s 18213.307us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 7.510s 2428.340us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 2.580s 367.724us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.850s 4494.961us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.300s 448.409us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.340s 513.318us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.400s 546.123us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 1572.210s 28865.779us 1 1 100.00
i2c_host_perf_precise 1.960s 273.595us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 15.220s 1703.998us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.570s 231.355us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.410s 1089.166us 1 1 100.00
i2c_target_nack_acqfull_addr 2.880s 3572.175us 1 1 100.00
i2c_target_nack_txstretch 1.660s 1799.711us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 12.460s 2189.209us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.560s 409.799us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.760s 20.897us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.960s 28.323us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.740s 567.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.740s 567.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.710s 86.335us 1 1 100.00
i2c_csr_rw 0.840s 26.920us 1 1 100.00
i2c_csr_aliasing 1.740s 118.401us 1 1 100.00
i2c_same_csr_outstanding 1.000s 26.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.710s 86.335us 1 1 100.00
i2c_csr_rw 0.840s 26.920us 1 1 100.00
i2c_csr_aliasing 1.740s 118.401us 1 1 100.00
i2c_same_csr_outstanding 1.000s 26.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.900s 125.653us 1 1 100.00
i2c_sec_cm 1.300s 66.001us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.900s 125.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 14.870s 3349.756us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.400s 128.462us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 7.720s 940.991us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 33715085625921090093465038994793982747060425324996579391059140156390728240711 131
UVM_ERROR @ 82179236 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 82179236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 84347475680035146835476812568185948031699743090869238702114703835959409703607 89
UVM_ERROR @ 940990623 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 940990623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 109046125091712842513527636540689586831756306154406690825804496347191801843326 78
UVM_ERROR @ 15054315 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 15054315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_stress_all 69518662719113844214868527490901716973492590369050693436491265344470782299137 128
UVM_ERROR @ 96896366628 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1799963
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 27547863715039414011554912231611343109457118075195838588008002411110441797511 81
UVM_ERROR @ 1805848546 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1805848546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 86561186755351197931095380991391357371426426228572708419487521104377936909843 75
UVM_ERROR @ 128461660 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 206 [0xce])
UVM_INFO @ 128461660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 3265517283135312638210217858714532265145249150078456679284275264262724989848 86
UVM_ERROR @ 3349755546 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3349755546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---