Simulation Results: kmac

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.78 %
  • code
  • 88.77 %
  • assert
  • 95.48 %
  • func
  • 91.08 %
  • line
  • 97.27 %
  • branch
  • 95.33 %
  • cond
  • 93.43 %
  • toggle
  • 99.96 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 38.960s 2699.641us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.930s 35.983us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 19.893us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 5.700s 590.652us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.380s 1029.869us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.460s 74.856us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 19.893us 1 1 100.00
kmac_csr_aliasing 3.380s 1029.869us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.720s 14.120us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.250s 69.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 229.700s 28112.505us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 404.320s 89314.324us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1456.900s 62244.773us 1 1 100.00
kmac_test_vectors_sha3_256 24.080s 2175.180us 1 1 100.00
kmac_test_vectors_sha3_384 20.150s 7261.359us 1 1 100.00
kmac_test_vectors_sha3_512 14.110s 733.788us 1 1 100.00
kmac_test_vectors_shake_128 121.850s 8901.380us 1 1 100.00
kmac_test_vectors_shake_256 215.490s 10843.047us 1 1 100.00
kmac_test_vectors_kmac 1.910s 55.921us 1 1 100.00
kmac_test_vectors_kmac_xof 2.180s 404.939us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 157.240s 13235.583us 1 1 100.00
app 1 1 100.00
kmac_app 13.800s 1369.527us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 84.540s 21838.135us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 126.730s 20182.566us 1 1 100.00
error 1 1 100.00
kmac_error 223.230s 13905.386us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 1.320s 450.638us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 21.670s 10141.036us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 9.690s 181.635us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 11.560s 3277.286us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 16.190s 2660.481us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.220s 253.613us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1379.580s 162032.042us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.970s 25.366us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.790s 32.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.920s 291.233us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.920s 291.233us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.930s 35.983us 1 1 100.00
kmac_csr_rw 0.890s 19.893us 1 1 100.00
kmac_csr_aliasing 3.380s 1029.869us 1 1 100.00
kmac_same_csr_outstanding 1.430s 44.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.930s 35.983us 1 1 100.00
kmac_csr_rw 0.890s 19.893us 1 1 100.00
kmac_csr_aliasing 3.380s 1029.869us 1 1 100.00
kmac_same_csr_outstanding 1.430s 44.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.030s 58.057us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.030s 58.057us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.030s 58.057us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.030s 58.057us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.550s 706.128us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 23.250s 2773.537us 1 1 100.00
kmac_tl_intg_err 1.730s 197.921us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.730s 197.921us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.220s 253.613us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 38.960s 2699.641us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 157.240s 13235.583us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.030s 58.057us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 23.250s 2773.537us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 23.250s 2773.537us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 23.250s 2773.537us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 38.960s 2699.641us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.220s 253.613us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 23.250s 2773.537us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 28.680s 3168.433us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 38.960s 2699.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 83.090s 17676.515us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 22233046263944567561274694750835073285729755671759322207598840567234767371672 79
UVM_FATAL @ 10141036281 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbe4fe000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10141036281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---