Simulation Results: lc_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.16 %
  • code
  • 88.70 %
  • assert
  • 95.99 %
  • func
  • 85.79 %
  • line
  • 97.58 %
  • branch
  • 96.13 %
  • cond
  • 79.10 %
  • toggle
  • 82.58 %
  • FSM
  • 88.10 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.100s 140.403us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 18.089us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.890s 23.794us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.280s 182.988us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 35.094us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 186.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.890s 23.794us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 35.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 6.030s 69.626us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 16.330s 5381.616us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 21.222us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.420s 268.243us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.710s 379.855us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_prog_failure 2.420s 268.243us 1 1 100.00
lc_ctrl_errors 8.710s 379.855us 1 1 100.00
lc_ctrl_security_escalation 5.700s 408.982us 1 1 100.00
lc_ctrl_jtag_state_failure 2.470s 51.962us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.040s 125.752us 1 1 100.00
lc_ctrl_jtag_errors 17.720s 22742.496us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.080s 749.760us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.650s 1330.991us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.040s 125.752us 1 1 100.00
lc_ctrl_jtag_errors 17.720s 22742.496us 1 1 100.00
lc_ctrl_jtag_access 9.210s 541.697us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.780s 954.049us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.920s 298.277us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.990s 1906.429us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.820s 1219.750us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.770s 1244.900us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.070s 166.362us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.150s 213.982us 1 1 100.00
lc_ctrl_jtag_alert_test 0.790s 88.530us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.510s 1047.312us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 62.380us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 7.080s 519.675us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.220s 18.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 221.652us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 221.652us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.089us 1 1 100.00
lc_ctrl_csr_rw 0.890s 23.794us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 35.094us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 148.094us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.089us 1 1 100.00
lc_ctrl_csr_rw 0.890s 23.794us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 35.094us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 148.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 66.020us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 66.020us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 16.330s 5381.616us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.270s 39.592us 0 1 0.00
lc_ctrl_sec_cm 6.250s 239.044us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.700s 408.982us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 6.030s 69.626us 0 1 0.00
lc_ctrl_jtag_state_post_trans 6.650s 1330.991us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.140s 310.223us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.140s 310.223us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.340s 390.459us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.520s 1315.033us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.520s 1315.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.410s 841.355us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 6036075322703691899902885090714273046916400972878880749557131247816607077389 383
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 39592215 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 39592215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 94586636706409264439728288193395217994041347009762469764413540108411779404108 729
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 69625686 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 69625686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 112430565550003224827272466203682344485001768465975670567805724078127360667716 281
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 51961716 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 51961716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 88114867201633922643366091775558174872432786588934272062278156886717005518391 450
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1330991338 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1330991338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 45565879601199505079565719469968714661598585966932315122691936144128680510825 842
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 519675021 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 519675021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51841049712288327332981260256621928099745703768354531759467750333717679323954 3682
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 841355391 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 841355391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---