Simulation Results: lc_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 89.93 %
  • assert
  • 95.99 %
  • func
  • 91.37 %
  • line
  • 97.50 %
  • branch
  • 95.80 %
  • cond
  • 79.63 %
  • toggle
  • 83.69 %
  • FSM
  • 93.02 %
Validation stages
V1
100.00%
V2
90.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.280s 27.224us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 46.473us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.890s 53.354us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 70.405us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 147.061us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.970s 38.561us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.890s 53.354us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 147.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.210s 5.031us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.710s 401.885us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 23.472us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 54.742us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.190s 212.981us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_prog_failure 1.970s 54.742us 1 1 100.00
lc_ctrl_errors 5.190s 212.981us 1 1 100.00
lc_ctrl_security_escalation 8.540s 788.847us 1 1 100.00
lc_ctrl_jtag_state_failure 7.660s 378.471us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.160s 772.394us 1 1 100.00
lc_ctrl_jtag_errors 41.370s 2331.051us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.900s 624.737us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.030s 1804.823us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.160s 772.394us 1 1 100.00
lc_ctrl_jtag_errors 41.370s 2331.051us 1 1 100.00
lc_ctrl_jtag_access 5.160s 2685.562us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.440s 1637.229us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.490s 90.003us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.590s 113.844us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.070s 546.699us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.220s 2083.390us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.910s 297.300us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.770s 199.061us 1 1 100.00
lc_ctrl_jtag_alert_test 1.080s 34.912us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.600s 1024.997us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 80.559us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 65.200s 12843.925us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 111.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.850s 920.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.850s 920.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 46.473us 1 1 100.00
lc_ctrl_csr_rw 0.890s 53.354us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 147.061us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.630s 51.013us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 46.473us 1 1 100.00
lc_ctrl_csr_rw 0.890s 53.354us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 147.061us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.630s 51.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 279.876us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 279.876us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.710s 401.885us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.580s 60.546us 0 1 0.00
lc_ctrl_sec_cm 6.420s 253.867us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.540s 788.847us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.210s 5.031us 0 1 0.00
lc_ctrl_jtag_state_post_trans 13.030s 1804.823us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.630s 567.761us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.630s 567.761us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.970s 613.331us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.700s 221.323us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.700s 221.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 8.340s 292.528us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 18594974278847577865109427169245097772288764630447659606236210898701434110369 653
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 60545983 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 60545983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 92151587202539747889638408177957679845844752379516322340690358672565698739018 121
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 5031173 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 5031173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 14899528438653571749731467946277537205261511581467006152979182601595469520844 752
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 378471181 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 378471181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98294458829241765309952702679897774997284534950545038836402875760327282850554 690
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 292527883 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 292527883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---