Simulation Results: otp_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.91 %
  • code
  • 72.22 %
  • assert
  • 91.13 %
  • func
  • 55.39 %
  • line
  • 87.15 %
  • branch
  • 82.46 %
  • cond
  • 84.98 %
  • toggle
  • 69.65 %
  • FSM
  • 36.84 %
Validation stages
V1
100.00%
V2
76.00%
V2S
53.57%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.150s 71.660us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.930s 478.499us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.670s 48.766us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.740s 320.927us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.200s 130.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.230s 98.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.670s 48.766us 1 1 100.00
otp_ctrl_csr_aliasing 7.200s 130.816us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.920s 45.142us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.160s 90.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 109.950s 4804.557us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.770s 79.335us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.970s 200.315us 0 1 0.00
otp_ctrl_check_fail 5.620s 263.820us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.660s 220.690us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 6.690s 435.446us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 8.640s 835.113us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 2.350s 38.729us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 8.440s 757.285us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 17.910s 3120.070us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 27.180s 2260.123us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.700s 621.266us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.380s 113.740us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.030s 184.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.030s 184.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.930s 478.499us 1 1 100.00
otp_ctrl_csr_rw 1.670s 48.766us 1 1 100.00
otp_ctrl_csr_aliasing 7.200s 130.816us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.850s 1511.806us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.930s 478.499us 1 1 100.00
otp_ctrl_csr_rw 1.670s 48.766us 1 1 100.00
otp_ctrl_csr_aliasing 7.200s 130.816us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.850s 1511.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 23.030s 1477.588us 1 1 100.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.030s 1477.588us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_macro_errs 8.440s 757.285us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_macro_errs 8.440s 757.285us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 286.602us 1 1 100.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.770s 79.335us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.620s 263.820us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 21.570s 7255.809us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 102.460s 65363.069us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.660s 220.690us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 15.060s 9476.392us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 8.440s 757.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 79.470s 22344.666us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.840s 147.424us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 62471743075386144610325541831319100232460705029589353714444996359455653382333 165244
UVM_ERROR @ 4804557207 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 4804557207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 39829376652642298598974837554088783502602998960872476083006347008582629806958 1584
UVM_ERROR @ 79334687 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 79334687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 37018387664550442715888233366229769445136442565591692378021130038664741982674 86
UVM_ERROR @ 22344666407 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 22344666407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 28737457514129004928853567286347705377227063481991965276165536528226686718639 1111
UVM_ERROR @ 200314842 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 200314842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 25009484918884419845603295976192549108005006989832534640704744399384471344728 159
UVM_ERROR @ 38729478 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 38729478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32974416908229164664565773391757012564520763565835473701475757886738833051909 5614
UVM_ERROR @ 263819548 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 263819548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 94336878177445098426667759909604370631057439188940889198746998608870694906525 88
UVM_ERROR @ 147423908 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 147423908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_stress_all 68212182376274087647937826246077659434235088193318935823426817825299690347192 20480
UVM_ERROR @ 2260122672 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 2260122672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 53075634197490453525787802084716836926416341428128668009991464217044348668449 977
UVM_ERROR @ 65363068968 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 65363068968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---