Simulation Results: rom_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.82 %
  • code
  • 99.29 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 99.49 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.330s 183.604us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.220s 174.009us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.050s 561.391us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.890s 535.889us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 128.455us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.320s 185.753us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.050s 561.391us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 128.455us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.090s 1076.165us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.660s 171.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.370s 176.506us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.060s 3045.658us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.240s 715.453us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.460s 127.233us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.930s 126.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.930s 126.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.220s 174.009us 1 1 100.00
rom_ctrl_csr_rw 3.050s 561.391us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 128.455us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.020s 570.014us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.220s 174.009us 1 1 100.00
rom_ctrl_csr_rw 3.050s 561.391us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 128.455us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.020s 570.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.190s 4460.854us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
rom_ctrl_tl_intg_err 42.820s 2330.687us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.330s 183.604us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.330s 183.604us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.330s 183.604us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.820s 2330.687us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
rom_ctrl_kmac_err_chk 6.240s 715.453us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.960s 38521.799us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.190s 4460.854us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 211.910s 1967.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 96.560s 16198.405us 1 1 100.00

Error Messages

   Test seed line log context