Simulation Results: rom_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.60 %
  • code
  • 98.13 %
  • assert
  • 95.49 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.61 %
  • toggle
  • 99.39 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 10.950s 313.402us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.090s 374.698us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.630s 1073.614us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.640s 701.827us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.550s 394.072us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.930s 3614.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.630s 1073.614us 1 1 100.00
rom_ctrl_csr_aliasing 6.550s 394.072us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.120s 726.117us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.460s 223.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 9.630s 383.328us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.420s 834.878us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.640s 552.326us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.440s 699.591us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.470s 301.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.470s 301.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.090s 374.698us 1 1 100.00
rom_ctrl_csr_rw 9.630s 1073.614us 1 1 100.00
rom_ctrl_csr_aliasing 6.550s 394.072us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.070s 300.611us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.090s 374.698us 1 1 100.00
rom_ctrl_csr_rw 9.630s 1073.614us 1 1 100.00
rom_ctrl_csr_aliasing 6.550s 394.072us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.070s 300.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.440s 20700.028us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 96.240s 869.707us 1 1 100.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 10.950s 313.402us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 10.950s 313.402us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 10.950s 313.402us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.240s 869.707us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
rom_ctrl_kmac_err_chk 15.640s 552.326us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.240s 84197.266us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.440s 20700.028us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 242.700s 1137.590us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 226.730s 4092.546us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 90609515073818633713668690621815509429376662415563085859417510907718998678684 364
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 97614704ps failed at 97614704ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 97614704ps failed at 97614704ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'