Simulation Results: rstmgr

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.72 %
  • code
  • 99.32 %
  • assert
  • 97.44 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.160s 69.249us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.280s 68.320us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.000s 67.167us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.120s 37.875us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.430s 65.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00
rstmgr_csr_aliasing 1.120s 37.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.910s 65.278us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.910s 43.286us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.320s 82.892us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.170s 558.503us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.170s 558.503us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.170s 558.503us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.170s 558.503us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.420s 2887.209us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.220s 37.246us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.700s 46.111us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.700s 46.111us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 68.320us 1 1 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00
rstmgr_csr_aliasing 1.120s 37.875us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 38.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 68.320us 1 1 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00
rstmgr_csr_aliasing 1.120s 37.875us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 38.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 3.840s 634.045us 1 1 100.00
rstmgr_sec_cm 32.530s 7043.255us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 32.530s 7043.255us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 32.530s 7043.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.840s 634.045us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 60.402us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.300s 415.030us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.020s 291.095us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 32.530s 7043.255us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 35.494us 1 1 100.00

Error Messages

   Test seed line log context