| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
33.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 0.690s | 51.384us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.560s | 62.263us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.540s | 17.304us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.710s | 68.564us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.610s | 274.858us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.550s | 39.154us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.540s | 17.304us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.610s | 274.858us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 1 | 100.00 | |||
| rv_timer_random_reset | 0.610s | 217.268us | 1 | 1 | 100.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 1.740s | 2343.531us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1.280s | 2289.963us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1.280s | 2289.963us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 3.720s | 2944.292us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.590s | 25.292us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.550s | 16.051us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.880s | 151.156us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.880s | 151.156us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.560s | 62.263us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.540s | 17.304us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.610s | 274.858us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.650s | 56.942us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.560s | 62.263us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.540s | 17.304us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.610s | 274.858us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.650s | 56.942us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 0.710s | 33.723us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 1.050s | 148.125us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 1.050s | 148.125us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 1 | 100.00 | |||
| rv_timer_min | 0.540s | 12.225us | 1 | 1 | 100.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.960s | 534.768us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_stress_all_with_rand_reset | 20.150s | 2450.319us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 51717415993947603703152624354985805205087705913187639265193490867254272703916 | 72 |
UVM_ERROR @ 534767554 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 534767554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 54603637172405459146445204031557372925150605998671586459519536713824355879134 | 253 |
UVM_ERROR @ 2450319102 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2450319102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|