Simulation Results: sram_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.22 %
  • code
  • 95.77 %
  • assert
  • 95.83 %
  • func
  • 94.06 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.04 %
  • toggle
  • 90.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 12.300s 3440.688us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.710s 111.790us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.660s 47.898us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 95.918us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 18.820us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.260s 1446.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.660s 47.898us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 18.820us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 121.830s 8982.087us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 116.550s 23172.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 1127.110s 46036.741us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 166.490s 22705.969us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1754.210s 34843.199us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 237.470s 43421.595us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 43.010s 52205.334us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 1035.530s 82010.425us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.300s 1426.542us 1 1 100.00
sram_ctrl_partial_access_b2b 260.590s 7758.331us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 13.870s 7170.730us 1 1 100.00
sram_ctrl_throughput_w_partial_write 20.590s 769.372us 1 1 100.00
sram_ctrl_throughput_w_readback 24.470s 3448.757us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 275.430s 1849.860us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.890s 1356.996us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3091.850s 181181.063us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.690s 39.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.360s 344.350us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.360s 344.350us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 111.790us 1 1 100.00
sram_ctrl_csr_rw 0.660s 47.898us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 18.820us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 38.485us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 111.790us 1 1 100.00
sram_ctrl_csr_rw 0.660s 47.898us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 18.820us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 38.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.430s 12832.598us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
sram_ctrl_tl_intg_err 1.250s 134.594us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.250s 134.594us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 275.430s 1849.860us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 275.430s 1849.860us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.660s 47.898us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 1035.530s 82010.425us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 1035.530s 82010.425us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 1035.530s 82010.425us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 43.010s 52205.334us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.920s 1358.942us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.430s 12832.598us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.360s 683.272us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 12.300s 3440.688us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 12.300s 3440.688us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 1035.530s 82010.425us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 43.010s 52205.334us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 12.300s 3440.688us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.660s 5.952us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.850s 4790.539us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 73877534375276195017531674140634218178112928284185431522615482228308634878319 96
UVM_ERROR @ 5952481 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5952481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---