Simulation Results: sram_ctrl

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.99 %
  • code
  • 90.32 %
  • assert
  • 95.51 %
  • func
  • 93.14 %
  • line
  • 97.68 %
  • branch
  • 95.96 %
  • cond
  • 91.43 %
  • toggle
  • 90.35 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 0.990s 141.544us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.660s 17.648us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 102.882us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.350s 137.162us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 62.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.320s 99.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 102.882us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 62.762us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.780s 237.652us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.410s 2875.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 609.010s 7922.425us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 165.360s 2475.485us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 14.370s 1759.702us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 422.040s 2020.531us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.890s 450.065us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 451.980s 3447.320us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.360s 217.129us 1 1 100.00
sram_ctrl_partial_access_b2b 330.200s 24001.070us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 17.780s 98.158us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.350s 80.985us 1 1 100.00
sram_ctrl_throughput_w_readback 17.340s 1000.419us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 279.210s 7297.805us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.690s 75.885us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1003.200s 6190.904us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.620s 21.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.380s 25.242us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.380s 25.242us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.660s 17.648us 1 1 100.00
sram_ctrl_csr_rw 0.710s 102.882us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 62.762us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.750s 48.061us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.660s 17.648us 1 1 100.00
sram_ctrl_csr_rw 0.710s 102.882us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 62.762us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.750s 48.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.500s 876.349us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
sram_ctrl_tl_intg_err 2.000s 931.627us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 931.627us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 279.210s 7297.805us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 279.210s 7297.805us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 102.882us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 451.980s 3447.320us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 451.980s 3447.320us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 451.980s 3447.320us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.890s 450.065us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.860s 41.897us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.500s 876.349us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.810s 36.647us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 0.990s 141.544us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 0.990s 141.544us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 451.980s 3447.320us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.890s 450.065us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 0.990s 141.544us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 1.415us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.450s 914.039us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 32456055926263789980689067499860821392818618048030787294437443595455280030126 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1414995 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1414995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---