Simulation Results: uart

 
09/12/2025 16:01:56 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.92 %
  • code
  • 95.52 %
  • assert
  • 97.12 %
  • func
  • 44.11 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 94.17 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.820s 90.279us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 16.448us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 14.805us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.300s 34.058us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.670s 16.253us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.270s 77.482us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 14.805us 1 1 100.00
uart_csr_aliasing 0.670s 16.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 13.230s 42855.147us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.820s 90.279us 1 1 100.00
uart_tx_rx 13.230s 42855.147us 1 1 100.00
parity_error 2 2 100.00
uart_intr 3.720s 9078.431us 1 1 100.00
uart_rx_parity_err 31.550s 52542.743us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 13.230s 42855.147us 1 1 100.00
uart_intr 3.720s 9078.431us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 91.880s 81814.033us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 34.400s 67238.532us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 21.410s 19645.166us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 3.720s 9078.431us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 3.720s 9078.431us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 3.720s 9078.431us 1 1 100.00
perf 1 1 100.00
uart_perf 246.040s 8250.566us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.440s 9921.781us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.440s 9921.781us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.730s 1401.310us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 51.410s 43439.559us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.700s 2169.655us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.510s 3911.320us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 511.090s 79620.904us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 17.650s 20876.397us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.640s 16.796us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.810s 14.264us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.710s 38.973us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.710s 38.973us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.448us 1 1 100.00
uart_csr_rw 0.580s 14.805us 1 1 100.00
uart_csr_aliasing 0.670s 16.253us 1 1 100.00
uart_same_csr_outstanding 0.630s 38.024us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.448us 1 1 100.00
uart_csr_rw 0.580s 14.805us 1 1 100.00
uart_csr_aliasing 0.670s 16.253us 1 1 100.00
uart_same_csr_outstanding 0.630s 38.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.270s 1476.037us 1 1 100.00
uart_sec_cm 0.950s 250.988us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.270s 1476.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 25.270s 8030.443us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 56328542941453393870080320748501817972842280283021968844548811653312162408021 72
UVM_ERROR @ 997070205 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12, clk_pulses: 0
UVM_ERROR @ 997084290 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 997168800 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1151498145 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 23, clk_pulses: 0
UVM_ERROR @ 1151512230 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_stress_all_with_rand_reset 97238051925570389609384044069688157371774897823455792394758866680273586236818 138
UVM_ERROR @ 7979082639 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7979562639 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7987802639 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7988922639 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7989842639 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 58136802634720063625803103484807317483721111410909489370280103343539946056282 78
UVM_ERROR @ 20838440478 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20839092648 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20839657862 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20840223076 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20841918718 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0