Simulation Results: aes

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.97 %
  • code
  • 94.69 %
  • assert
  • 98.36 %
  • func
  • 76.86 %
  • block
  • 95.66 %
  • line
  • 97.12 %
  • branch
  • 90.33 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 60.984us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 111.829us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 69.976us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.029us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 328.635us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 70.335us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 107.057us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.029us 1 1 100.00
aes_csr_aliasing 2.000s 70.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 111.829us 1 1 100.00
aes_config_error 3.000s 340.816us 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 111.829us 1 1 100.00
aes_config_error 3.000s 340.816us 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 140.338us 1 1 100.00
aes_b2b 18.000s 1986.177us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 111.829us 1 1 100.00
aes_config_error 3.000s 340.816us 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 52.791us 1 1 100.00
aes_config_error 3.000s 340.816us 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 8.000s 2624.669us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 44.000s 9576.086us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 140.338us 1 1 100.00
aes_sideload 2.000s 68.745us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 364.724us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 127.000s 12690.199us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 65.532us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 251.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 251.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.976us 1 1 100.00
aes_csr_rw 2.000s 77.029us 1 1 100.00
aes_csr_aliasing 2.000s 70.335us 1 1 100.00
aes_same_csr_outstanding 3.000s 311.312us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.976us 1 1 100.00
aes_csr_rw 2.000s 77.029us 1 1 100.00
aes_csr_aliasing 2.000s 70.335us 1 1 100.00
aes_same_csr_outstanding 3.000s 311.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 78.527us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 729.757us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 146.815us 1 1 100.00
aes_sec_cm 4.000s 863.706us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 146.815us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 111.829us 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
aes_core_fi 3.000s 223.506us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.646us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 155.224us 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 140.338us 1 1 100.00
aes_sideload 2.000s 68.745us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 155.224us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 155.224us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 155.224us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 155.224us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 155.224us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 140.338us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 615.104us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 615.104us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 615.104us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 113.817us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_ctr_fi 2.000s 69.046us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 615.104us 1 1 100.00
aes_control_fi 2.000s 50.888us 1 1 100.00
aes_cipher_fi 2.000s 88.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 1232.695us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 87167909413161788957741219889740856652197814261628788679922444358569081746283 580
UVM_ERROR @ 1232695203 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1232695203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---