Simulation Results: alert_handler

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.80 %
  • code
  • 91.57 %
  • assert
  • 98.20 %
  • func
  • 76.63 %
  • line
  • 99.71 %
  • branch
  • 99.77 %
  • cond
  • 93.58 %
  • toggle
  • 92.21 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
91.67%
V2S
96.30%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.120s 77.537us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.420s 135.945us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 315.460s 14034.984us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 224.500s 4973.263us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.550s 131.196us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.420s 135.945us 1 1 100.00
alert_handler_csr_aliasing 224.500s 4973.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 36.810s 7510.019us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 8.480s 371.081us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 952.450s 95175.251us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 30.280s 952.797us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 28.770s 1898.495us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 9.410s 221.192us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 18.150s 817.374us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 195.130s 3384.199us 0 1 0.00
alert_handler_lpg_stub_clk 953.600s 60230.938us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2102.160s 98983.071us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 31.250s 1047.156us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.690s 14.608us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.470s 6.845us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 7.360s 530.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 7.360s 530.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.120s 77.537us 1 1 100.00
alert_handler_csr_rw 4.420s 135.945us 1 1 100.00
alert_handler_csr_aliasing 224.500s 4973.263us 1 1 100.00
alert_handler_same_csr_outstanding 35.650s 2277.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.120s 77.537us 1 1 100.00
alert_handler_csr_rw 4.420s 135.945us 1 1 100.00
alert_handler_csr_aliasing 224.500s 4973.263us 1 1 100.00
alert_handler_same_csr_outstanding 35.650s 2277.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 158.740s 2352.074us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 158.740s 2352.074us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 158.740s 2352.074us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 158.740s 2352.074us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 528.090s 9699.655us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 66.180s 4253.738us 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 66.180s 4253.738us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 158.740s 2352.074us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 27.630s 578.112us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 30.280s 952.797us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 195.130s 3384.199us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 30.280s 952.797us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 952.450s 95175.251us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 952.450s 95175.251us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 18.180s 471.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 5.800s 384.195us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 44740722104536172463009397896446380278310458964959064117473244442255095058742 78
UVM_ERROR @ 817374121 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 817374121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_*
alert_handler_lpg 83324703946891154933762775623496345188130109243455911160395070017864770117749 77
UVM_ERROR @ 3384198960 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0
UVM_INFO @ 3384198960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 50669192827974405050216346179110978397008054298424675267865665176548028374269 79
UVM_ERROR @ 384195117 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 384195117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---