| V1 |
|
33.33% |
| V2 |
|
32.97% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
36.84% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 120.147s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 120.147s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 102.009s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 88.407s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 299.770s | 268.703us | 1 | 1 | 100.00 | |
| chip_sw_gpio_in | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 299.770s | 268.703us | 1 | 1 | 100.00 | |
| chip_sw_gpio_irq | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 299.770s | 268.703us | 1 | 1 | 100.00 | |
| chip_sw_example_tests | 1 | 4 | 25.00 | |||
| chip_sw_example_rom | 29.290s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 143.319s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 148.130s | 150.378us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest_signed | 9.477s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 10.350s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 8.660s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 8.660s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 20.890s | 63.317us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 103.738s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 1 | 1 | 100.00 | |||
| chip_sw_spi_device_pass_through | 2767.580s | 5216.541us | 1 | 1 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 191.640s | 186.920us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 61.294s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 59.367s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 79.060s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 76.632s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 3.900s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 3.900s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 142.217s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 121.479s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 168.773s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 168.773s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 110.600s | 117.050us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 109.130s | 117.032us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 229.470s | 272.647us | 1 | 1 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 11.630s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 9.688s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 142.760s | 249.932us | 0 | 1 | 0.00 | |
| chip_sw_timer | 1 | 1 | 100.00 | |||
| chip_sw_rv_timer_irq | 223.260s | 248.744us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 427.200s | 526.541us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 427.200s | 526.541us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 345.630s | 348.270us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 207.160s | 164.328us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 207.160s | 164.328us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 294.880s | 2271.461us | 1 | 1 | 100.00 | |
| chip_sw_plic_sw_irq | 1 | 1 | 100.00 | |||
| chip_sw_plic_sw_irq | 163.170s | 145.502us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 4 | 4 | 100.00 | |||
| chip_sw_otbn_randomness | 268.350s | 225.626us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 145.510s | 147.268us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_idle | 183.850s | 161.524us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 151.470s | 145.058us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 154.470s | 165.680us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 162.840s | 165.664us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 166.000s | 165.648us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 160.290s | 165.648us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 42.890s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 37.100s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 35.090s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 36.870s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.450s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.671s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 146.380s | 141.895us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_extended_range | 1 | 8 | 12.50 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 300.960s | 1779.487us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 37.050s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 37.690s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 45.680s | 10.140us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 40.790s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 36.420s | 10.220us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 40.830s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 36.400s | 10.300us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 9.653s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 11.591s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 11.467s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 339.800s | 500.837us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 207.160s | 164.328us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 9.511s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 339.800s | 500.837us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 18.829s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 9.875s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.346s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 20.052s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 9.983s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 229.470s | 272.647us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 376.170s | 374.992us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 256.910s | 267.096us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 324.720s | 289.789us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 154.080s | 144.138us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 10.249s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 10.352s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 9.281s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 324.720s | 289.789us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 1 | 1 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 269.610s | 331.706us | 1 | 1 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.573s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 10.232s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 9.872s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 9.313s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 10.299s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 10.352s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 24.565s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_prod | 258.710s | 267.416us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 2 | 10 | 20.00 | |||
| chip_prim_tl_access | 81.790s | 151.354us | 1 | 1 | 100.00 | |
| chip_rv_dm_lc_disabled | 142.760s | 249.932us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.205s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 52.048s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 27.613s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 44.263s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 255.050s | 267.420us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 717.690s | 1266.485us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 10.139s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 169.740s | 157.107us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 37.100s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 1 | 1 | 100.00 | |||
| chip_sw_aes_entropy | 145.740s | 145.869us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1 | 1 | 100.00 | |||
| chip_sw_aes_idle | 145.510s | 147.268us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc | 1 | 2 | 50.00 | |||
| chip_sw_hmac_enc | 164.660s | 156.433us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 35.090s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_hmac_enc_idle | 183.850s | 161.524us | 1 | 1 | 100.00 | |
| chip_sw_kmac_enc | 2 | 3 | 66.67 | |||
| chip_sw_kmac_mode_cshake | 171.800s | 148.913us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac | 187.250s | 172.110us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.450s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 255.050s | 267.420us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 36.270s | 10.280us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 1 | 1 | 100.00 | |||
| chip_sw_kmac_entropy | 254.710s | 206.392us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_kmac_idle | 151.470s | 145.058us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_csrng | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 366.670s | 282.164us | 1 | 1 | 100.00 | |
| chip_sw_csrng_edn_cmd | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 366.670s | 282.164us | 1 | 1 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 27.463s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 1 | 1 | 100.00 | |||
| chip_sw_csrng_kat_test | 170.150s | 156.794us | 1 | 1 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1 | 1 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 803.820s | 683.911us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0 | 2 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 255.050s | 267.420us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 36.870s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 1 | 2 | 50.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 2271.370s | 1467.496us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 42.890s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 268.350s | 225.626us | 1 | 1 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 268.350s | 225.626us | 1 | 1 | 100.00 | |
| chip_sw_otbn_idle | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 268.350s | 225.626us | 1 | 1 | 100.00 | |
| chip_sw_otbn_mem_scramble | 1 | 1 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 359.860s | 264.727us | 1 | 1 | 100.00 | |
| chip_sw_rom_access | 1 | 1 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 717.690s | 1266.485us | 1 | 1 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 1 | 1 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 717.690s | 1266.485us | 1 | 1 | 100.00 | |
| chip_sw_sram_scrambled_access | 1 | 2 | 50.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 298.470s | 322.168us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.671s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 10.139s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 168.773s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 3 | 4 | 75.00 | |||
| chip_sw_otbn_mem_scramble | 359.860s | 264.727us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 255.050s | 267.420us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 298.470s | 322.168us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 151.740s | 161.014us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 3 | 4 | 75.00 | |||
| chip_sw_otbn_mem_scramble | 359.860s | 264.727us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 255.050s | 267.420us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 298.470s | 322.168us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 151.740s | 161.014us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 9.957s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 24.565s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 1 | 6 | 16.67 | |||
| chip_prim_tl_access | 81.790s | 151.354us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.205s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 52.048s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 27.613s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 44.263s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 24.159s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 1 | 1 | 100.00 | |||
| chip_prim_tl_access | 81.790s | 151.354us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 30.892s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 13.538s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 9.653s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 42.890s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 37.100s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 35.090s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 36.870s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.450s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.671s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 146.380s | 141.895us | 1 | 1 | 100.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 147.540s | 137.296us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 147.540s | 137.296us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 152.730s | 138.816us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_gpios | 144.220s | 136.442us | 0 | 1 | 0.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 302.630s | 251.575us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_rnd | 220.950s | 176.591us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_address_translation | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 177.500s | 164.793us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 151.740s | 161.014us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 376.170s | 374.992us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 376.170s | 374.992us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 14 | 14 | 100.00 | |||
| chip_sw_aes_smoketest | 146.540s | 157.123us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_smoketest | 153.220s | 163.239us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_smoketest | 129.060s | 143.015us | 1 | 1 | 100.00 | |
| chip_sw_csrng_smoketest | 127.500s | 144.789us | 1 | 1 | 100.00 | |
| chip_sw_gpio_smoketest | 136.610s | 174.053us | 1 | 1 | 100.00 | |
| chip_sw_hmac_smoketest | 166.340s | 182.002us | 1 | 1 | 100.00 | |
| chip_sw_kmac_smoketest | 154.000s | 171.133us | 1 | 1 | 100.00 | |
| chip_sw_otbn_smoketest | 167.530s | 191.520us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_smoketest | 130.770s | 146.944us | 1 | 1 | 100.00 | |
| chip_sw_rv_plic_smoketest | 122.320s | 145.040us | 1 | 1 | 100.00 | |
| chip_sw_rv_timer_smoketest | 186.430s | 248.731us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_smoketest | 120.540s | 141.625us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 131.510s | 145.484us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest | 131.120s | 157.826us | 1 | 1 | 100.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 11.381s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 9.477s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 103.738s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 10.601s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 4 | 4 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 205.690s | 211.877us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 166.100s | 222.352us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 189.600s | 218.395us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 184.550s | 226.125us | 1 | 1 | 100.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_rv_dm_lc_disabled | 142.760s | 249.932us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 10.317s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 22.985s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 14.441s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 9.209s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 9.291s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 10.317s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 2 | 3 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 471.400s | 630.913us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 432.610s | 578.221us | 1 | 1 | 100.00 | |
| rom_volatile_raw_unlock | 10.365s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 9.590s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 107.488s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 123.146s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 104.390s | 118.030us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 104.390s | 118.030us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 8.660s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 8.930s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 8.660s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 8.930s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 41.570s | 100.966us | 1 | 1 | 100.00 | |
| xbar_random_delay | 6 | 6 | 100.00 | |||
| xbar_smoke_zero_delays | 10.150s | 13.772us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 295.340s | 2442.528us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 326.370s | 1943.255us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 19.990s | 21.514us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 1422.420s | 12115.383us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 1796.080s | 10940.969us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 63.760s | 37.899us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 37.490s | 27.289us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 22.070s | 23.740us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 37.490s | 27.289us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 142.910s | 313.734us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 450.310s | 2509.684us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 47.600s | 141.313us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 328.800s | 839.664us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 126.840s | 402.950us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 1129.740s | 410.878us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 805.130s | 714.576us | 1 | 1 | 100.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 10.625s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 10.184s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 9.832s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 10.152s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 10.250s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 9.664s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 10.177s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 10.689s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 9.932s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 9.702s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 9.599s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 8.975s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.191s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 67.483s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 63.415s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 62.659s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 58.918s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 53.914s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 49.985s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 68.755s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 61.177s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 63.337s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 44.924s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 64.515s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 50.627s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 61.357s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 48.111s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 54.964s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 12.313s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 12.560s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 13.144s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 11.348s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 9.546s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 9.302s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 10.838s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 16.291s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 10.333s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 9.943s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 9.462s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 10.263s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 9.561s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 9.504s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 1 | 1 | 100.00 | |||
| chip_sw_aes_masking_off | 186.820s | 173.974us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 147.270s | 136.617us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 10.046s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 9.971s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 12.862s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 9.700s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 862.670s | 905.277us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 13.172s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 170.280s | 158.132us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 10.450s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 10.382s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 10.046s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 9.971s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 12.862s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 12.543s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 9.842s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 10.053s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 9.864s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 7 | 19 | 36.84 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 851.220s | 905.217us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_kat_test | 149.930s | 144.285us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 146.110s | 141.604us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_0 | 400.770s | 346.695us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_10 | 324.970s | 302.147us | 1 | 1 | 100.00 | |
| chip_sw_dma_inline_hashing | 161.690s | 189.761us | 1 | 1 | 100.00 | |
| chip_sw_dma_abort | 187.860s | 192.935us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 10.067s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 9.772s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 10.261s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 9.779s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 9.106s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 9.274s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 9.349s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 9.322s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 9.761s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 9.629s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 160.200s | 178.914us | 1 | 1 | 100.00 | |
| chip_sw_mbx_smoketest | 222.790s | 292.301us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' | ||||
| chip_tl_errors | 34103875970341723298989076133765488390777616166782917136030669599222372826733 | 229 |
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.030000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.030000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | ||||
| chip_rv_dm_lc_disabled | 60948326171414743674840762084158054616562086773585981477516350768822240631320 | 210 |
UVM_ERROR @ 249.932000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406ac read out mismatch
UVM_INFO @ 249.932000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[CNST-CIF] Constraints inconsistency failure | ||||
| chip_padctrl_attributes | 47700950370450922596643886348140660686798418879627301253560977179986244420412 | 278 |
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode | ||||
| chip_csr_bit_bash | 56850336376679647509120335501790904052170589258499669372326250409595557020409 | 133 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_aliasing | 23429279238096330919541915647260627147072501561893674734094581993160419423224 | 133 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_same_csr_outstanding | 65038738251521535550279398219129074389781121597285845000832557885969925364152 | 133 |
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode | ||||
| chip_sw_example_rom | 94663340177599309693670684228263928691213779395656801100888752528319426370345 | 573 |
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job returned non-zero exit code | ||||
| chip_sw_example_manufacturer | 16569841853969502405988990861664831976472601444341393392621877664302588278257 | None |
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 133.676s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_data_integrity_escalation | 71569626206124419488949157345279381804755159952011074559239948757422852588617 | None |
Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 158.440s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_sleep_pin_wake | 90302208006844776905513642831980629009614162266632282335656030898007091580988 | None |
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 132.213s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_sleep_pin_retention | 25602534723337108844715140456149140910099025039128657618771637612280879098140 | None |
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 111.682s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx | 8168549662778412643445053222608411697656663185103649162983657060121177276344 | None |
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 110.765s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_bootstrap | 93341172223534766347915571049431230682706106932574414515948878977910142226903 | None |
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 94.179s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_inject_scramble_seed | 4039749481611119731600263788476901661710880665644480133226103955861756160089 | None |
Analyzing: target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 114.254s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_exit_test_unlocked_bootstrap | 94431477292761967386888655262091891479671301774334836042682748619955045703322 | None |
Analyzing: target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 98.680s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_uart_rand_baudrate | 115149833166288840771509812093388962923647364928954277863645868521299740281085 | None |
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 93.646s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_alt_clk_freq | 115215651828958906044624183518334056194531597113140436025287420887517405143394 | None |
Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 80.219s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_i2c_host_tx_rx | 67482783515968534643234667435159993345315891867419095168460946336464003835374 | None |
Analyzing: target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 70.674s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_i2c_device_tx_rx | 22397100807839582699452452473306784853915856448556358503218636630296211658460 | None |
Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 68.449s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_spi_device_tpm | 5095682143022287679357716930697061245769168632668123004230054435243095674727 | None |
Analyzing: target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 50.241s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_spi_host_tx_rx | 76140581202904992781907511758178123801822163284357989175485491171735955653671 | None |
Analyzing: target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 51.193s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_otp_hw_cfg | 32999159349931083452410297827897883441799037421504476267306489101433332597967 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
INFO: Elapsed time: 16.118s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 52327184059548243434608841397441072978064312380848086149310601083914173561874 | None |
Analyzing: target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.614s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_dev | 10543984246693745121865002132742722233692050970201570451307322735508992604967 | None |
Analyzing: target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 43.501s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_prod | 26516368945768263362427151626437836200819142302839578089706498081001285329508 | None |
Analyzing: target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 19.169s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 62366135971656143114631995636145567871192864285306718031281262196341901787863 | None |
Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 35.669s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_vendor_test_csr_access | 83624878578327510289371657809262671640529099027411122435227571598469283459900 | None |
Analyzing: target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.710s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_nvm_cnt | 86957081230408504848683286503841080244315651624325125408602443222948608067557 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 22.624s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_sw_parts | 31090519327429172245255168542002687288078316897456359074735379743334220155473 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 5.047s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_transition | 49046760299781388651450863055579224392649809136725668351435845189298664743793 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 15.674s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_dev | 66679519892651069976285619171466472538466128722611003635205110101593397454399 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 14.136s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prod | 102896113800844908052357448700231284493248325062715511881261355819240595060912 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.726s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prodend | 101582346595692155614957417150348931338138923696285405185260396496693392509365 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.674s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_rma | 65947201395364567498347593385822951169583575864924678247816813025036555217889 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.565s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_testunlocks | 111871953811921217406164785545926777376778273507462919317723471335956783242979 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.592s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_main_power_glitch_reset | 41428675409277731670954458060084007636778435411132461118942722748413725363574 | None |
Analyzing: target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.772s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 86602105045576425860683806709115244540398491413925398320395854611808621610167 | None |
Analyzing: target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 11.140s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 34902786403191851819392790050498423036036643205563434519590296996624047081674 | None |
Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.252s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1890522479759513607531217827070729725530762010196261031692056493054478519307 | None |
Analyzing: target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.196s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_disabled | 15982191683948279218676731781021910112424461090172526648370056573242370967874 | None |
Analyzing: target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.186s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_pwrmgr_wdog_reset | 54914880467703283000840753881974766545502554285458122385938779426676662137240 | None |
Analyzing: target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.221s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_test | 5063464200957272215722161404674444389176645111001990413649531766479764497392 | None |
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
INFO: Elapsed time: 0.151s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_escalation | 10820180606360996903729136335758423411974205831968811176415563750719880797012 | None |
Target //sw/device/tests:alert_handler_escalation_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.918s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 28350368961757844769698653011228764719337332098239624103140109979818287747160 | None |
Analyzing: target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.879s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81009437822542842793615112674605562497075225639470243122260026473332881690945 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.148s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_pings | 25006513997664001648467458475614711204617088192378933314214401282126256976741 | None |
Analyzing: target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.240s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_clkoff | 30584628804562739045355993479746324885135561802488911841208426787368246856532 | None |
Analyzing: target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.176s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_reset_toggle | 48686296472538603556898519748929747394392342010264639194071935652648076354161 | None |
Analyzing: target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.159s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_alert_handler_entropy | 62806253109724510669305508022617942867974800599335261672913168834728177615748 | None |
Analyzing: target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.164s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 42861905528632339665639697425148224364411527082042656889765165998320426094872 | None |
Analyzing: target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 17.283s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 82196010643896735915391338542628282886722124537611890146157123661533194053678 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
INFO: Elapsed time: 0.136s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_execution_main | 78951832678789615804782725625086457169035760908755816017033565631313848448680 | None |
Analyzing: target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.236s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_coremark | 82683552912770717940413788498802088853877253296321315943223357942525623691158 | None |
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
INFO: Elapsed time: 0.185s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_clkmgr_reset_frequency | 17967249149515853240329233113425958172762166766108561472351812697012609086967 | None |
Analyzing: target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.082s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_clkmgr_sleep_frequency | 76859621049480985179636401735645283768986253043664836965014835153942539694878 | None |
Analyzing: target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.029s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_ast_clk_outputs | 52275917558382870021083664207879767827393933927819892482676478740879321187751 | None |
Analyzing: target //sw/device/tests:ast_clk_outs_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.199s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_program_error | 56788355854688548476245820175624995267942900709670242810705549083003765547170 | None |
Analyzing: target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.185s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 68854345880702316631163957863828061942078883228500008520781136889205778276054 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
INFO: Elapsed time: 1.734s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_wakeup | 94945208869728362433133149464885322494418340108698185548143144438439357695117 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
INFO: Elapsed time: 0.435s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_escalation_reset | 25266620656443608987966529935735069791330721117556289579078990689637161076702 | None |
Analyzing: target //sw/device/tests:alert_handler_escalation_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.219s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_power_virus | 103680466496950634467538664771235449138045884955628489573253121161587368566567 | None |
Analyzing: target //sw/device/tests:power_virus_systemtest_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.230s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| base_rom_e2e_smoke | 77195384137444558142634101146449501790099325783374052758494472865189213612253 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke_sim_dv': target 'base_rom_e2e_smoke_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke_sim_dv': target 'base_rom_e2e_smoke_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.738s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_smoke | 51691168235588192211715483242532662979632480010489298440103832777408964667484 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.404s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_shutdown_exception_c | 105960115500879728299721553395586226481408918035526577800502381654978745879971 | None |
Analyzing: target //sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.233s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_shutdown_output | 98287713193479401624465731087584952269244918454636480663137012178810584945626 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.186s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 63698717430338084792850896970893616563555789414057276280560857327200899258743 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.139s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 53773739874882040772844352600590681781125113134268787951943827599164185391006 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.133s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 100939634902536949417976656648211909467155577118346422693632028440887814420620 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.263s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 39452772745472679683585534962647739794809923419184829252222658874471298990308 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.131s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 39980717386404664847559762583187784093188124727258395245013165951587935537101 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.138s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 81627234421505342357834505483463603064671380543906537010251264487101598405337 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.231s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 68330171505144602226848971722632957801762202340374133650508809804836902570815 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.289s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 73095171556502365088584659122250399592349931849494868960595488849368524706075 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.139s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 55130292591086098132714923996388495680610154286340464732874245976665291233801 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.145s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 64700206201115036167548254237715481090110463708607559089508418268992868638650 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 2.010s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 77953692474839102532780543075737490425758037600043138148215942012747262653837 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.594s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 61453344626697696426678070699132890456332423922650512322790443382417165269295 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.070s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2761000556685519385709770578453273241220730012474179104885009509995722492487 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.570s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 68311352058111461135099497610181811649937520759147729133653114197259760199813 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 4.074s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 20656465428766678762006059621472799964355720021567233895457192185526588430018 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.109s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 59981163116593086752315929464555304296324616439559831827046162648000595616938 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 2.432s, Critical Path: 0.20s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 108643131240835164070271183803619162402752477952812350312506405433372662383360 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 1.365s, Critical Path: 0.23s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 45614906959497164472435459585556580714711922214096317200283360159597679561478 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 1.470s, Critical Path: 0.24s
INFO: 4 processes: 1878 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 51762081434773405750823385929318498628799979481819556201461885481049569685094 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 0.905s, Critical Path: 0.22s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 93367907882424548899361673320020147671675251654727081682002849285299121227436 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 0.805s, Critical Path: 0.22s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 41228890910678267978229070381634855180061152809612483573400575325832870537364 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.478s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 73133686937298564421889299936451592865903411254578249461978678469620399565543 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 15.632s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 46447376583908984070325270649873568998881560817955153694599862574600953243258 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.657s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 88977017900040685108619683016947533365007514703939709216410648354768393015417 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 2.076s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 69815754834963353980085965331605382208263065268828369483687543392550234509583 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 3.025s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 89148963015621636786416853878505576862528328279130476550203768153818374971324 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 3.400s, Critical Path: 0.24s
INFO: 8 processes: 1879 action cache hit, 4 internal, 4 processwrapper-sandbox.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 105897941170538921578604712491240847445555632678518499194071023024597327453155 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 3.847s, Critical Path: 0.21s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 10079102334348095094296585709588091182240136076425413958318512196003470508278 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 4.399s, Critical Path: 0.20s
INFO: 4 processes: 1880 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 31010954793338859845456374714541682767162024555270310231382075179499366590192 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 2.679s, Critical Path: 0.08s
INFO: 4 processes: 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 108911641471971639686524717076717122470674767637020085822811616373372656006236 | None |
riscv32-unknown-elf-ld.lld: error: bazel-out/k8-fastbuild-ST-1df456420242/bin/sw/device/lib/testing/test_framework/ottf_ld_silicon_creator_slot_b.ld:11: cannot find linker script hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
>>> ^
clang-16: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Target //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 0.902s, Critical Path: 0.20s
INFO: 4 processes: 1883 action cache hit, 4 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 78757272778276771562794743979928872011846139581946153521605437452948064049013 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.618s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 6912700935110113923464919083592969311678174761213122995752486097186157114858 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 2.073s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 86260872658096398163248803074498399188487982738868954769615372939004528000065 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 7.627s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 62295365592117486885083691749899183145300353354335557144024501561680292336271 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.628s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 84352433775924808677021387759697378822716297769693907991766833723720931598791 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.142s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 25127718517588394371514464532823009518447737552604391460038264543775815351594 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.157s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_dev | 9264781567806356001318183511342564199916970816940856706184044286778084963796 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.175s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_rma | 43586860749827372165136554727650313527994513960022343918898013647817602593034 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 4.128s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 84107483308335579553895237838582516962952666062415968064244697003225801196263 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 3.547s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 10223886480375239652664137541279143765442191133216318750791471186029877357990 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.139s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 71729210086999490870357652131273191620425726042241779779783379975432930898869 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.157s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_static_critical | 45451857851033761704813295750822842512264625698888945621940421697442433611854 | None |
Analyzing: target //sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.642s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_meas | 53092953098427037502601642744578395295991309556753711229376848741711073670666 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.629s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 94805571095623429883925960937364425969956208777023757919711033152806003023405 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.463s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 20993530775987493002797211894936168421952641277561030998085251414963081509879 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.595s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 58700347267258197935325501952136296573125446071980257403112811599101608941697 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.127s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 58690435395558852441570620797013563780391707174547770967472308171925572466700 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.627s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_otbn | 8890698043441124694000436779398076025505308876821152561768383128353211455605 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 1.055s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_sw | 66066752854804616778717112109602005285142200438160243003998349132769842378324 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.490s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_otbn | 67440717270748999109368990419202574441421057864929885829996487058283462899434 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.146s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_sw | 91750901191893069528412793695648010138382723257044342066736847003583105773864 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.172s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 83078967952162726535847140074345627204703915139393357929201206434302466057673 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.155s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_sw | 97161019086250063798506533447746610974427750656903084846747471584457704079961 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.165s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_otbn | 77015340157954961191078897829086545057544870144933250878157872857780041540437 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.159s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_sw | 40431189988670238612716214007950790947067063906380637433127103188448737491995 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.145s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 103116104846486192155815810355466343750599044833203746933095762275979623596271 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.303s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_raw_unlock | 29663124401098519288990168352155340460818511657637816392700845101222624326174 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
INFO: Elapsed time: 0.153s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_e2e_self_hash | 4161422939777764695845470753067658655237390325094020832061609358591994495890 | None |
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash_sim_dv (5fdbd2)
//sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash_sim_dv_scr_vmem64 (623923)
//hw/top_earlgrey/data/otp:img_test_unlocked0 (623923)
//hw/top_earlgrey/data/otp:otp_json_test_unlocked0 (623923) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.293s, Critical Path: 0.06s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| chip_sw_uart_smoketest_signed | 109596976524424837346185464614703620197073095260587083950180263157523892953511 | None |
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.131s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| rom_keymgr_functest | 72569172306517113911001900600006214968921682786636895442194249646357548548996 | None |
Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.701s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size | ||||
| chip_sw_all_escalation_resets | 75246112118524046184456319209450421400142441324296053144034645320793556863082 | 469 |
UVM_ERROR @ 905.277000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.277000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 29782976667037695843913002422302199242987304915359775053700879246584521329035 | 490 |
UVM_ERROR @ 905.217000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.217000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | ||||
| chip_sw_spi_device_pass_through_collision | 20175207706118309392135231768691456835973053820916636889228444306635542203957 | 476 |
UVM_ERROR @ 186.920000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 186.920000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | ||||
| chip_sw_otp_ctrl_escalation | 44566391971820977013479650430979653267919110261642068638497795041621621979606 | 433 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.132000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.132000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size | ||||
| chip_sw_rstmgr_alert_info | 12828204902870303604856730164600424581506698630550128563269456781563505735341 | 436 |
UVM_ERROR @ 289.789000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.789000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!rstreqs[*]) && (reset_cause != HwReq))' | ||||
| chip_sw_rstmgr_cpu_info | 109804507216172836334472309680248559923039787895212096599240028687024997330924 | 427 |
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 374.992000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 374.992000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_aes_trans | 57834287173709129187396842850725066644729967118837070196827699560070387811737 | 402 |
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_hmac_trans | 94274019599540508117725997272986680226970032762734771249962048628597500787253 | 415 |
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_kmac_trans | 44669123582589163894470545532431765863684599348017067571495781377493347770792 | 410 |
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_otbn_trans | 66735752828034166130432617446648808171798834325307798079682968114110609010336 | 394 |
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! | ||||
| chip_sw_soc_proxy_smoketest | 14261088278336944217034489991806689849792700853144373615940384755719602944655 | 397 |
UVM_ERROR @ 137.296000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 137.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * | ||||
| chip_sw_soc_proxy_external_wakeup | 72878359682567309772632834249354440617696696756062379379306701608739334022521 | 389 |
UVM_ERROR @ 138.816000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.816000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * | ||||
| chip_sw_soc_proxy_gpios | 108767148973847705289180559610632895430763157266729619479794216651963010033810 | 394 |
UVM_ERROR @ 136.442000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.442000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec | ||||
| chip_sw_aon_timer_irq | 73110307525050442281253006615376545089078774474400854150335073533779347662830 | 389 |
UVM_ERROR @ 526.541000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3845 usec which is not in the range 351 usec and 402 usec
UVM_INFO @ 526.541000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds | ||||
| chip_sw_aon_timer_wdog_bite_reset | 95070176707885532858607336514384667954646959889795890159668740907252407326051 | 388 |
UVM_ERROR @ 164.328000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" | ||||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 22936311880989446740943262433588947441993573975776220612423662477743744723035 | 383 |
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en | 31239860995244881570916917754075061367416573825996994775876354017108095174566 | 375 |
UVM_FATAL @ 10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en | 29530121475915069731300145223476826131900323555444730509138889372727453597371 | 400 |
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_keymgr_dpe_key_derivation_jitter_en | 57126387885422315898998847946981631142363530303299977813578427843848371799674 | 377 |
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_kmac_mode_kmac_jitter_en | 97320461690476292087535709043041003275837972948380622888615833531668748880807 | 385 |
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 90932142126187958811256360678496235680125858991332168618846411980124976753311 | 395 |
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_aes_enc_jitter_en_reduced_freq | 50873453198461318385435141758751610920644980348229921884097672807945132593136 | 396 |
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_hmac_enc_jitter_en_reduced_freq | 68693002286716126359565262834865939147165503733496198820628349362056663117877 | 380 |
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 57010101188110946963237687142521298981629170397317731991593410357998256673114 | 379 |
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 51335318273805372656581867650105597271804613960437114968603412305142349548448 | 386 |
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 99590709625143907211458548745224859651040474226559594445825921637131577228035 | 381 |
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_csrng_edn_concurrency_reduced_freq | 99013778406628196649664464698281695299727179314178179707055027348407195357647 | 380 |
UVM_FATAL @ 10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * | ||||
| chip_sw_rv_core_ibex_rnd | 31742641850257455999052917696740411855794394615546213516222219314560506136589 | 390 |
UVM_ERROR @ 176.591000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
UVM_INFO @ 176.591000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired | ||||
| chip_sw_rv_core_ibex_nmi_irq | 84250300690718444286130206184030308571869723105860361715767130460272839446201 | 394 |
UVM_ERROR @ 251.575000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.575000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP | ||||
| chip_sw_keymgr_dpe_key_derivation | 90291554829985489590781012792651501316912595248128572732794007921882033989150 | 412 |
UVM_ERROR @ 267.420000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3352444992953055116510892532431216700718448848083726666636680291748072899569073758261290708938946837071150694781668371937373621689383486153445520231980124 [0x400268e7aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3c654d8167f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.420000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_keymgr_dpe_key_derivation_prod | 11223128406719414161067884331893551204163994299871699030785999303440359295490 | 404 |
UVM_ERROR @ 267.416000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4010526388610364079556322524227906904791310875512706408112524502819857965862980687669793364771632204411566798764583571692554443002017173504568558778408028 [0x4c930b6daae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3cac5bb9c7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.416000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode | ||||
| chip_sw_kmac_app_rom | 41557189329703675402950160381396191786671712010603600861988990070749156710655 | 394 |
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } | ||||
| chip_jtag_csr_rw | 109865691784388524468143441613833494507688094550743709390395202004326159294127 | 5959 |
UVM_ERROR @ 117.050000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'hd605c1c4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h1 a_user: 'h24880 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.050000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_jtag_mem_access | 33963105062257648936891908303732583271080490125396076995098320966656462646743 | 5959 |
UVM_ERROR @ 117.032000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'h1842bb2e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h1 a_user: 'h248fa d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.032000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * | ||||
| chip_sw_dma_abort | 55250422092050061262694038922778558132068411616242492232159741970008128581817 | 392 |
UVM_ERROR @ 192.935000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.935000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|